XRT72L53 Datasheet, PDF (12/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L53
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.7
PIN DESCRIPTION CONNECTED PINS
PIN #
C12
PIN NAME
RxOH[0]/
RxHDLCDat6[0]
C13
TxOHFrame[0]/
TxHDLCClk[0]
TYPE
O
O
DESCRIPTION
Receive Overhead Data Output/Receive HDLC Data Output - Bit 6;
Channel 0:
The exact function of this input pin depends upon whether Channel 0
has been configured to operate in the High Speed HDLC Controller
Mode, or not.
Non-High Speed HDLC Controller Mode - Receive Overhead Data
Output - Channel 0:
All overhead bits, which are received via the Receive Section of the
Framer IC; will be output via this output pin, upon the rising edge of
RxOHClk.
High Speed HDLC Controller Mode - Receive HDLC Data Output -
Bit 6:
This pin functions as bit 6, within the byte-wide Receive HDLC Control-
ler input interface (RxHDLCDat[7:0]), whenever Channel 0 has been
configured to operate in the “High-Speed HDLC Controller” Mode.
Transmit Overhead Data Framing Pulse/Transmit HDLC Output
Clock - Channel 0:
The exact function of this input pin depends upon whether Channel 0
has been configured to operate in the High-Speed HDLC Controller
Mode, or not.
Non-High Speed HDLC Controller Mode - Transmit Overhead Data
Framing Pulse:
This output pin pulses "High" when the Transmit Overhead Data Input
Interface block is expecting the first Overhead bit, within a DS3 or E3
frame to be applied to the TxOH input pin.
This pin is "High" for one clock period of TxOHClk.
High-Speed HDLC Controller Mode -Transmit HDLC Output Clock:
This pin functions as a demand and latching clock for the Transmit
HDLC Controller input interface, when Channel 0 has been configured
to operate in the “High-Speed HDLC Controller” Mode.
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