XRT72L53 Datasheet, PDF (140/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

áç THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
XRT72L53
REV. P1.1.7
and will then branch program control to the Framer in-
terrupt service routine. In the case of Figure 37, the
interrupt service routine will be located in 0x0003 in
code memory. The 8051 CPU does not issue an In-
terrupt Acknowledge signal back to the Framer IC. It
will just begin processing through the Framer’s inter-
rupt service routine. One the CPU has eliminated the
cause(s) of the interrupt request, the Framer’s INT
output pin will be negated (e.g., go "High”) and the
CPU will return from the Interrupt Service Routine
and resume normal operation.
2.9 INTERFACING THE FRAMER IC TO A MOTOROLA-
TYPE MICROPROCESSOR
This section discusses how to interface the
XRT72L53 DS3/E3 Framer IC to the MC68000 Micro-
processor.
Figure 38 presents a schematic on how to interface
the XRT72L53 DS3/E3 Framer IC to the MC68000
Microprocessor, over an 8-bit wide bi-directional data
bus.
FIGURE 38. SCHEMATIC DEPICTING HOW TO INTERFACE THE XRT72L53 DS3/E3 FRAMER IC TO THE MC68000
MICROPROCESSOR
U5
18
RESET
R/W
DTACK
9
10
D0
D1
D2
D3
D4
5
4
3
2
1
64
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
63
62
61
60
59
58
57
56
55
54
IPL0
25
24
IPL1 ₂₃
IPL2
VPA ²¹
FC0
FC1
FC2
28
27
26
AS
6
7
UDS
LDS
8
29
A1
A2
A3
A4
A5
A6
A7
A8
30
31
32
33
34
35
36
37
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
38
39
40
41
42
43
44
45
46
47
48
49
50
A22
A23
51
MC68000
D[15:8]
U9
HPRI/BIN
15
14
9
7
6
1 - 10
- 11
18
-
-
12
13
- 14
- 15
- 16
1 ^{- 17}
2
4
0/Z10
1/Z11
2/Z12
3/Z13
4/Z14
5/Z15
6/Z16
7/Z17
V18
EN
10
11
12
13
1
2
3
4
5
74HC148
XRT72L53 INTERRUPT REQUEST
DATA_STROBE*
ADDRESS_STROBE*
U10
5V
1
2
3
6
4
5
BIN/OCT
1
2
4
& EN
0
1
2
3
4
5
6
7
15
14
13
12
11
10
9
7
74ACT138
ADDRESS_STROBE*
DATA_STROBE*
U12A ₁
& ³
2
74AHCT00
1 4 U 1 3 B 3
74HC04
U13A
74HC04
From Address Decoder
3.3V
DECODED FUNCTION CODE
U11
BIN/OCT
5V
1
2
3
1
2
4
6
4
5 ^{& EN}
0
1
2
3
4
5
6
7
15
14
13
12
11
10
9
7
74ACT138
To Address Decoder
U6
T19
P17
J17
RESET
WRB_RW
Rdy_Dtck
L18
L20
K20
K19
K18
D0
D1
D2
D3
K17
J20
J19
D4
D5
D6
D7
V20
R19
RDB_DS
ALE_AS
R20
P18
P19
A0
A1
P20 ^A2
N18
N19
N20
M17
M18
M19
M20
A3
A4
A5
A6
A7
A8
A9
A10
H20 _INT
R18 _CS
T20 _MOTO/INTEL
XRT72L53
In general, the approach to interfacing these two de-
vices is straightforward. However, the XRT72L53
DS3/E3 Framer IC does not provide an interrupt vec-
tor to the MC68000 during an Interrupt Acknowledge
cycle. Therefore, the design must be configured to
support auto-vectored interrupts. Auto-vectored inter-
rupt processing is a feature offered by the MC68000
Family of Microprocessors, where, if the microproces-
sor knows (prior to any IACK cycle) the Interrupt Lev-
el of this current interrupt, and that the interrupting
peripheral does not support vectored interrupts, then
the Microprocessor will generate its own Interrupt
Vector. The schematic shown in Figure 38, has been
configured to support auto-vectored interrupts.
Functional Description of Circuit illustrated in
Figure 38.
When the XRT72L53 DS3/E3 Framer IC generates
an Interrupt, the INT output will toggle "Low”. This will
force Input 6, of the Interrupt Priority Encoder chip
140