XRT72L53 Datasheet, PDF (320/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

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PRELIMINARY
XRT72L53
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.8
RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Not Used
FERF
Interrupt
Status
RO
RO
RO
RO
RUR
0
0
0
0
0
BIT 2
BIP-4
Error
Interrupt
Status
RUR
1
Finally, the Receive E3 Framer block will increment
the PMON Parity Error Count registers. The byte for-
mat of these registers are presented below.
PMON PARITY ERROR COUNT REGISTER - MSB (ADDRESS = 0X54)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Parity Error Count - High Byte
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
BIT 1
Framing
Error
Interrupt
Status
RUR
0
BIT 0
Not Used
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
PMON PARITY ERROR COUNT REGISTER - LSB (ADDRESS = 0X55)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Parity Error Count - Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
BIT 1
RUR
0
BIT 0
RUR
0
The user can determine the number of BIP-4 Errors
that have been detected by the Receive E3 Framer
block, since the last read of these registers. These
registers are reset-upon-read.
Configuring the XRT72L53 Framer IC to support
BIP-4 Error Detection
In order to perform BIP-4 checking of each E3 frame,
the user must configure the XRT72L53 Framer IC ac-
cordingly, by executing the following steps.
1. Configure the Transmit Section (of the XRT72L53
Framer IC) to insert the BIP-4 value into the out-
bound E3 frames. This is accomplished by writing
a “1” into bit-field 7 (Tx BIP-4 Enable) within the
TxE3 Configuration Register, as illustrated below.
TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Tx
BIP-4
Enable
TxASourceSel[1:0]
TxNSourceSel[1:0]
R/W
R/W
R/W
R/W
R/W
1
0
0
0
0
BIT 2
Tx AIS
Enable
R/W
0
BIT 1
Tx LOS
Enable
R/W
0
BIT 0
Tx FAS
Source
Select
R/W
0
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