XRT72L53 Datasheet, PDF (121/467 Pages) Exar Corporation – THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER

XRT72L53
REV. P1.1.7
THREE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
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PRELIMINARY
data, immediately following any string of 5 consecu-
tive "1’s".
• Read in this stuffed PMDL Message from the Trans-
mit LAPD Message buffer, and encapsulate it into a
LAPD Message frame.
• Fragment the resulting LAPD Message frame into
octets.
• Insert these octets into either the GC byte-field or
the NR byte-field (depending upon the user's selec-
tion) in each outbound E3 frame.
A "0" to "1" transition, in this bit-field commands the
LAPD Transmitter to initiate the above-mentioned
procedure.
NOTE: Once the user has commanded the LAPD Transmit-
ter to start transmission, the LAPD Transmitter will repeat
the above-mentioned process once each second and will
insert flag sequence octets into the outbound LAPD chan-
nel, during the idle periods between transmissions.
Bit 2 - TxDL Busy
This Read-Only bit-field is used to poll or monitor the
status of the LAPD Transmitter to see if it has com-
pleted its transmission of the LAPD Message frame.
The LAPD Transmitter will set this bit-field to "1",
while it is in the process of transmitting the LAPD
Message frame. However, the LAPD Transmitter will
clear this bit-field to "0" once it has completed its
transmission of the LAPD Message frame.
Bit 1 - TxLAPD Interrupt Enable
This Read/Write bit-field is used to enable or disable
the LAPD Message frame Transmission Complete in-
terrupt.
Writing a "0" to this bit-field disables this interrupt.
Writing a "1" to this bit-field enables this interrupt.
Bit 0 - TxLAPD Interrupt Status
This Reset-upon-Read bit-field is used to determine if
the LAPD Message Frame Transmission Complete in-
terrupt has occurred since the last read of this regis-
ter. If this bit-field contains a "1" then the LAPD Mes-
sage Frame Transmission Complete interrupt has oc-
curred since the last read of this register. Conversely,
if this bit-field contains a "0" then it has not.
2.4.7.4 Transmit E3 Service Bits Register (ITU-
T G.751)
TXE3 SERVICE BITS REGISTER (ADDRESS = 0X35)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
A Bit
N Bit
RO
RO
RO
RO
RO
RO
R/W
R/W
0
0
0
0
0
0
1
0
Bit 1 - A Bit
This Read/Write bit-field is used to define the value of
the A Bit within a given outbound E3 frame. If the user
has configured the source of the A Bit to be the TxE3
Service Bits Register (by setting TxASource[1:0] =
00, within the TxE3 Configuration Register, Address =
0x30), then the value written in this bit-field will speci-
fy the value of the A Bit within the outbound E3
Frame.
Bit 0 - N Bit
This Read/Write bit-field is used to define the value of
the N Bit within a given outbound E3 frame. If the us-
er has configured the source of the N Bit to be the
TxE3 Service Bits Register (by setting TxN-
Source[1:0] = 00, within the TxE3 Configuration Reg-
ister, Address = 0x30), then the value written in this
bit-field will specify the value of the N Bit within the
outbound E3 Frame.
2.4.7.5 Transmit E3 FAS Mask Register - 0
(ITU-T G.751)
TXE3 FAS ERROR MASK REGISTER - 0 (ADDRESS = 0X48)
BIT 7
RO
0
BIT 6
Not Used
RO
0
BIT 5
RO
0
BIT 4
R/W
0
BIT 3
BIT 2
BIT 1
TxFAS_Error_Mask_Upper[4:0]
R/W
R/W
R/W
0
0
0
BIT 0
R/W
0
Bits 4 - 0, TxFAS_Error_Mask_Upper[4:0]
This Read/Write bit-field is used to insert errors into
the upper five bits of the Framing Alignment Signal,
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