CN8330 Datasheet, PDF (95/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
Appendix A Multimegabit HDLC Formatter
Control Registers
0x05—PPDL Control Register (CRO5)
The PPDL Control Register is provided to control the mode of operation of the PPDL transmitter and receiver.
NOTE: Rsvd bits in Control Registers must be set to zero.
7
FCSCnt[3]
FCSCnt[3:0]
LimitFCS
CRC32
6
5
4
3
2
1
FCSCnt[2] FCSCnt[1] FCSCnt[0]
LimitFCS
CRC32
Rsvd
0
Rsvd
FCS Calculation Count—Determines the number of bytes over which the FCS is to be calcu-
lated. The number of bytes for calculation can be from 1 to 16 (a value of zero defaults to 16
bytes of calculation).
Limit FCS Calculation—Set to enable FCS calculation only on the first N bytes of an HDLC
frame where N is determined by the FCS calculate count field. If this bit is low, the FCS will
be calculated over all transmitted bytes.
32-Bit CRC Select—Set high to enable 32-bit CRC generation and checking on the PPDL. If
this bit is low, then 16-bit CRC generation and checking is enabled.
100441E
Conexant
A-11