CN8330 Datasheet, PDF (54/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

2.0 Functional Description
2.4 Receiver Operation
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
The parallel interface can be used without transparency bit deletion by setting
the DisPPDL bit in the PPDL Control Register to a 1. In this mode, byte
synchronization in the transmitter and receiver is achieved from the M-frame sync
alignment and zeros detected after strings of five ones are not deleted. This allows
the byte-wide interface to be used as the data output in normal DS3/E3 mode
rather than the serial output pin. The IDLE/FRMCAR and VALFCS/TXOVH
indications are ignored when operating in this mode. Data bytes are received with
the same timing relative to RXBCK/RXGAPCK as in HDLC mode. In E3 mode,
190 bytes per frame will be received with byte alignment after the 16 overhead
bits (FAS, A, N, 1100).
The PPDL receiver can be used with a nibble-wide interface for DS3 SMDS
applications if desired. To enable nibble-wide transmission, both the Nibble Mode
Enable and DisPPDL bit controls in the PPDL Control Register should be set to 1.
Received data is available on the least significant nibble of the RDAT[7:0] pins
with the same timing relative to RXBCK/RXGAPCK (which now occurs every 4
bits). In nibble mode, the nibbles are received MSB first, with the MSB on
RDAT[3], 2SB on RDAT[2], 1SB on RDAT[1], and the LSB on RDAT[0]. For E3
SMDS applications, the byte-wide interface should be used.
FCS checking can be limited to the first N bytes of the received message by
setting the LimitFCS control bit in the PPDL Control Register. In this mode, the
FCS is checked only on the first N bytes received after the opening flag and then
held until the end of the message. The locally calculated FCS is then compared to
the last two/four bytes in the message to determine if a valid FCS was received.
The desired number N can be from 1 to 16 (a value of 0 gives N = 16) and is
loaded in the FCSCnt[3:0] control field in the PPDL Control Register. This
allows FCS checking only on the header information in a T1 packet voice format.
2.4.9 PPDLONLY Mode
The receiver can be placed in a mode where the entire receive stream is expected
to be data with no DS3/E3 overhead bits inserted. This mode is enabled by
providing a high input on the PPDLONLY input pin. This mode allows the IC to
be used as a high-speed PPDL receiver and can be used at any clock rate up to the
full 52 MHz capability of the device. This data interface is described in the PPDL
Receiver section of this chapter.
2-32
Conexant
100441E