CN8330 Datasheet, PDF (65/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
3.0 Registers
3.2 Status Registers
0x11—Counter Interrupt Status Register (SR01)
The Counter Interrupt Status Register contains status information about active interrupts needing service from
the controller. This register needs to be read by the controller upon receiving a counter interrupt to determine the
source of the interrupt. The interrupt indications are active high in the register and are available even if they are
not enabled to be visible on the CNTINT/LINELB output pin. Servicing will clear this interrupt indication as
described in Microprocessor Interrupts in the Microprocessor Interface section in the Functional Description
chapter. Counter operation is discussed in DS3/E3 Error Counters in the Status Registers section of this chapter.
NOTE(S): Rsvd bits in Control Registers must be set to zero.
7
Rsvd
ShdwItr
LCVCtrItr
FEBECtrItr
PthCtrItr
FerrCtrItr
DgrCtrItr
ParCtrItr
6
ShdwItr
5
LCVCtrItr
4
FEBECtrItr
3
PthCtrItr
2
FerrCtrItr
1
DgrCtrItr
0
ParCtrlltr
Shadow Status Register Interrupt—Set if any of the bits in the Shadow Status Register get set.
This bit is cleared by reading the Shadow Status Register [SR06;0x16].
LCV Counter Interrupt—Set high on an LCV error counter roll-over or saturation. The LCV
Counter Interrupt Enable bit [LCVCtrIE;CR02.5] determines the status of the counter. This bit
is cleared when this status register is read.
FEBE Event Counter Interrupt—Set high if the FEBE event counter has either rolled over or is
saturated. The FEBE Event Counter Interrupt Enable [FEBECtrIE;CR02.4] determines the
status of the counter. This bit is cleared when this status register is read.
Path Parity Error Counter Interrupt—Set high if the path parity error counter has either rolled
over or is saturated. The Parity Error Counter Interrupt Enable bit [PthCtrIE.CR02.3]
determines the status of the counter. This bit is cleared when this status register is read.
Frame Error Counter Interrupt—Set high when the frame error counter has either rolled over
or is saturated. The Frame Error Counter Interrupt Enable [FerrCtrIE;CR02.2] determines the
status of the counter. This bit is cleared when this status register is read.
Disagreement Counter Interrupt—Set high if the disagreement counters have either rolled over
or are saturated. The Disagreement Counter Interrupt Enable bit [DgrCtrIE;CR02.1]
determines the status of the counter. This bit is cleared when this status register is read.
Parity Error Counter Interrupt—Set high if the parity error counter has either rolled over or is
saturated. The Parity Error Counter Interrupt Enable bit [ParCtrIE;CR02.0] determines the
status of the counter. This bit is cleared when this status register is read.
100441E
Conexant
3-7