CN8330 Datasheet, PDF (94/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

Appendix A Multimegabit HDLC Formatter
Control Registers
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
Control Registers
0x00—Mode Control Register (CR00)
NOTE: Rsvd bits in Control Registers must be set to zero.
7
LineLp
LineLp
SourceLp
6
5
4
3
2
1
0
SourceLP
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Line Loopback Enable—Set to enable the loopback in the external direction. This loopback
connects the received data stream before B3ZS/HDB3 decoding to the transmitter outputs. The
received data is still presented to all receiver blocks and is present on the receiver output pins.
Source Loopback Enable—Set to enable the loopback in the internal direction. This loopback
connects the encoded transmitter data and clock directly to the receiver. Transmission of data
on the line is not affected by this loopback.
0x04—Feature Control Register (CR04)
The Feature Control Register is provided to enable or disable miscellaneous features in the CN8330 Framer.
NOTE: Rsvd bits in Control Registers must be set to zero.
7
Rsvd
ParaEn
6
5
4
3
2
1
0
Rsvd
Rsvd
Rsvd
ParaEn
Rsvd
Rsvd
Rsvd
Parallel Data Enable—Set high to enable the PPDL transmitter and receiver as the source and
sink for data. Eight-bit data bytes are provided on the TDAT[7:0] and RDAT[7:0] buses for the
PPDL transmitter and receiver. This bit must be set to 1 for operation as an HDLC formatter.
A-10
Conexant
100441E