CN8330 Datasheet, PDF (49/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
2.0 Functional Description
2.4 Receiver Operation
The receiver powers up in an indeterminate state. It is initialized by the receipt
of an idle flag (0x7E) on the link, which sets RxIdle = 1 in the Terminal Data Link
Status Register. When the idle flag is removed from the link and a message starts
coming in, the receiver removes stuffed zeros and writes the resulting data to the
Receive Terminal Data Link Message Buffer beginning with address 0x40 and
counting up to 0x47.
When the first four addresses have been written, the processor is interrupted
to read the data out of the buffer. The processor has four byte intervals (at least 1
msec) to read the data before it is overwritten with new data. The interrupt is
cleared when the processor reads the Terminal Data Link Register. This register
will indicate a message in progress at this time (RxIdle = 0, RxByte[2:0] = 3). If
the upper half of the buffer had just been filled, the status register will indicate
RxByte[2:0] = 111 and locations 4 through 7 must be read during the next four
byte intervals to retrieve the message.
When the last block of data has been received, the processor will again be
interrupted. This time the Terminal Data Link Status Register will indicate the
end of message (RxIdle = 1, RxByte[2:0] = n, BadFCS = 0 or 1). The
RxByte[2:0] = n portion of the register indicates the highest numbered location
that was written in the receive buffer. Locations 0 to n or 4 to m (where n = 0 to 3
and m = 4 to 7) must be read to retrieve the data depending on what has already
been read at the previous interrupt. The two highest numbered locations contain
the FCS that was received at the end of the message. A new incoming message
will always start in the opposite buffer half from where the previous message
ended to prevent overwriting of previously received bytes and allow the processor
time to retrieve those bytes. For example, if a message ended in buffer address
0x44, 0x45, 0x46, or 0x47, the next message received would be stored beginning
in address 0x40. If a message ended in buffer address 0x40, 0x41, 0x42, or 0x43,
the next message received would be stored beginning in address 0x44.
If the received message is a multiple of 8 bytes, then when the processor is
interrupted to read the last block of data, the FCS has yet to be received. In this
event, the processor will again be interrupted when the FCS has been checked and
an idle flag is received. The Terminal Data Link Status Register will show
RxByte[2:0] = 001 (or 101), BadFCS = 0 or 1, and RxIdle = 1; and the FCS
received will be in locations 0 and 1 (or 4 and 5). Again, the data must be read out
during the next four byte intervals, or it may be overwritten by a new incoming
message. Alternatively, the FCS data may be ignored, and the good or bad
indication used directly. It is important that software strategies allow for the fact
that the LAPD receiver cannot recognize the FCS as such until the closing flag is
recognized. It can happen that the processor is interrupted to read four message
bytes, and the next byte received is the closing flag. When the processor exits the
interrupt routine, another interrupt will be pending for the end of message. The
status for this interrupt will indicate the idle condition, the FCS status, and the
byte count will be the same as the previous interrupt (RxByte[2:0] = 011 or 111)
because no extra bytes were received. In this event, the last two bytes read from
memory on the previous interrupt were not message bytes after all, but were
actually the FCS bytes. If the FCS spans a 4-byte boundary, the final interrupt
will indicate the idle condition, the FCS status, and that one additional byte was
received (RxByte[2:0] = 000 or 100).
100441E
Conexant
2-27