CN8330 Datasheet, PDF (21/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
Table 1-2. Hardware Signal Definitions (4 of 5)
Pin Label
Signal Name
DS3CKI
DS3 Receive Line Clock In
RXPOS, RXNEG
Receive Bipolar
Positive/Negative
RXCKI
Receive Dejittered
Clock In
FIFEN
FIFO Enable
RXDAT
Receive Serial Data
RXMSY
Receive M-Sync
RXCLK
Receive Clock
RXBCK/RXGAPCK Receive Byte/Gapped Clock
CBITO
Receive C/N-Bit Serial Out
RXCCK/TXNRZ
RDAT[0]/LOS
Receive C/N-Bit Clock
Out/Transmit NRZ
Receive Data Byte 0/Loss of
Signal
RDAT[1]/OOF
Receive Data Byte 1/
Out of Frame
RDAT[2]/AIS
Receive Data Byte 2/Alarm
Indication Signal
1.0 Product Description
1.1 Pin Descriptions
I/O
Definition
I Clock input DS3CKI should be connected to a 44.736
MHz source (34.368 MHz for the E3) derived from
incoming receive data.
I The input positive and negative pulses are sampled
on the rising edge of the receiver input clock
(DS3CKI) and should be a full clock period wide.
I Used to read the received data out of the internal
FIFO (required only if FIFO is enabled). If unused, tie
to ground.
I
An active-high input which enables the internal
FIFO, used to dejitter the received data by using the
dejittered clock input, RXCKI. When FIFEN is low, the
FIFO is bypassed and the serial data is output with
respect to the incoming clock, DS3CKI.
O RXDAT is the serial data bit stream clocked out on
the rising edge of RXCLK.
O The M-frame synchronization output recovered from
the incoming serial data stream.
O The receive clock used internally to clock out the
serial data stream onto RXDAT.
O When in serial mode, RXGAPCK provides a gapped
clock signal during every overhead bit (in both DS3
and E3 modes). In parallel mode, RXBCK is used to
internally clock out the receive byte-oriented data on
RDAT[7:0].
O The receive serial C-bit (DS3 mode) or N-bit (E3
mode) data. CBITO changes on the rising edge of
RXCCK.
O A clock that indicates transitions in the CBIT0 signal.
In PPDL-only mode, transmit NRZ data is available
on this pin.
O Part of the 8-bit data bus output from the PPDL
receiver when parallel mode is enabled. When
parallel mode is disabled, this pin is an active-high
monitor output indicating loss of signal.
O Part of the 8-bit data bus output from the PPDL
receiver when parallel mode is enabled. When
parallel mode is disabled, this pin is an active-high
monitor output indicating out-of-frame.
O Part of the 8-bit data bus output from the PPDL
receiver when parallel mode is enabled. When
parallel mode is disabled, this pin is an active-high
monitor output indicating alarm indication signal.
100441E
Conexant
1-11