CN8330 Datasheet, PDF (25/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
2.0 Functional Description
2.1 Overview
2.1.2 Clock Interface and Initialization
2.1.2.1 Initialization
The CN8330 clock input (TXCKI) controls the transmitter. This input should be
supplied with a 44.736 MHz clock in DS3 mode and a 34.368 MHz clock in E3
mode. TDAT[6]/TXDATI is sampled on the falling edge of TXCKI and
TDAT[7]/TXSYI is sampled on the rising edge of TXCKI. The transmit pulses
TXPOS and TXNEG are clocked out on the rising edge of TCLKO.
DS3CKI is the raw data clock that accompanies the RXPOS and RXNEG data
pulse inputs for the receiver. If the FIFO buffer is enabled, the data is clocked into
the FIFO buffer after B3ZS/HDB3 decoding. RXCKI is the dejittered version of
DS3CKI and is used to clock the receive data out of the FIFO buffer (if enabled)
to the rest of the receiver circuitry. If the FIFO buffer is disabled, DS3CKI clocks
the data into all of the receiver circuitry and the RXCKI input should be
grounded.
Clock timing requirements are given in the Electrical and Mechanical
Specifications chapter.
The CN8330 can be initialized with an active-low input pulse of at least 200 ns
duration on the INIT* pin. All error counters are initialized to zero when this
input is active low if the transmit and receive clocks are present. Initialization is
not required for proper operation. During initialization (active low) host cannot
read or write any CN8330.
2.1.3 Microprocessor Interface
2.1.3.1 Using with
Specific Microcontrollers
The CN8330 can be controlled by a microprocessor or a microcontroller through
an 8-bit multiplexed address/data interface. An interface to an Intel 8051 family
processor or equivalent, or Motorola 68HC11 family or equivalent is provided.
The microprocessor interface is enabled by tying the MON/MIC* pin low. The
CN8330 is connected to the microprocessor exactly like static RAM.
The microprocessor interface is designed to allow direct connection of Intel 8051
family, Motorola 68HC11 family, or equivalent microcontrollers. The controller
interface to the CN8330 consists of 14 pins: Address Latch Enable (ALE), Read
Enable (RD*), Write Enable (WR*), Chip Select (CS), eight multiplexed
address/data bits (AD[7:0]), and two interrupts (DLINT/SOURCELB and
CNTINT/LINELB). If a 68HC11 controller is used, then its address strobe as is
connected to ALE, Enable is connected to RD*, and Read/Write* (R/W*) is
connected to WR*. The chip select input (CS/ALM0) allows the control of
multiple ICs from a single microprocessor. Interrupt outputs are used for data link
and maintenance operations and provide active-low interrupts.
100441E
Conexant
2-3