CN8330 Datasheet, PDF (63/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
3.0 Registers
3.1 Control Registers
FEBEC[3:1]
FEBE Pattern Bit Field—Set to the 3-bit sequence that is to be sent each time a FEBE
indication is to be transmitted in C-bit parity mode. This pattern is automatically transmitted
when the receiver detects an F-bit or path parity error. The pattern must be anything other than
all ones to indicate a FEBE to the far end. An all-ones pattern will disable FEBE transmission
and should not be used for any other purpose.
0x05—PPDL Control Register (CR05)
The PPDL Control Register is provided to control the mode of operation of the PPDL transmitter and receiver.
7
FCSCnt[3]
FCSCnt[3:0]
LimitFCS
CRC32
DisPPDL
Nibble
6
FCSCnt[2]
5
FCSCnt[1]
4
FCSCnt[0]
3
LimitFCS
2
CRC32
1
DisPPDL
0
Nibble
Frame Check Sequence Calculation Count—Determines the number of bytes over which the
FCS is to be calculated. The number of bytes for calculation can be from 1 to 16 (a value of 0
results in 16 bytes of calculation).
Limit Frame Check Sequence Calculation—Set to enable FCS calculation only on the first N
bytes of an HDLC frame where N is determined by the FCS Calculation Count field. If this bit
is low, the FCS will be calculated over all transmitted bytes.
32-Bit Cycle Redundancy Check—Set high to enable 32-bit CRC generation and checking on
the PPDL. If this bit is low, then 16-bit CRC generation and checking is enabled.
Disable PPDL Transparency Bit—Set high to disable insertion and removal of HDLC
transparency bits in the PPDL transmitter and receiver. If this control bit is low, then normal
insertion and removal of HDLC transparency bits will occur.
Nibble Mode Enable—Set to enable the nibble mode interface to the PPDL transmitter and
receiver for use in DS3 SMDS/802.6 applications. The Disable PPDL Transparency bit should
be set high when nibble mode is enabled.
100441E
Conexant
3-5