CN8330 Datasheet, PDF (69/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
3.0 Registers
3.2 Status Registers
0x20–0x26—DS3/E3 Error Counters
There are six error counters for DS3/E3 errors located at addresses 0x20–0x26. All are 8-bit counters with the
exception of the DS3 Disagreement [SR08;0x21] and DS3/E3 LCV Counters [SR12,SR13;0x25,0x26]. The
8-bit counters indicate 0 through 255 counts of a particular error. If the interrupt for a particular counter is not
enabled, the counter will saturate at 255 when more than 255 counts of that error are received and the saturation
indication will appear in the Counter Interrupt Status Register [SR01;0x01]. The saturation indication and the
counter will be cleared when the counter is read. If the interrupt for a particular counter is enabled in the
Interrupt Control Register [CR02; 0x02], then the counter will not saturate but will roll over and continue
counting from zero. An interrupt will be generated on the CNTINT/LINELB output pin and will appear in the
Counter Interrupt Status Register when the counter rolls over to a count of zero. The interrupt will be cleared
when the Counter Interrupt Status Register is read.
The only valid counters in E3 mode are the DS3/E3 LCV and Frame Error Counters. The DS3/E3 Frame
Error Counter [SR09;0x22] counts each occurrence of an incorrect pattern in the 10-bit FAS.
All counters are cleared when read by the microprocessor. The interrupt indication for a particular counter is
also cleared when the counter is read. Both nibbles of the DS3 Disagreement Counter [SR08;0x21] are cleared
when address 0x21 is read. Each byte of the DS3/E3 LCV Counter is cleared separately when it is read.
Software should read the low byte first and then the high byte to prevent any missed counts. All counters are
designed so that errors occurring during reads by the microprocessor will not be missed or double-counted. All
counters except for LCV and Frame Error are frozen during an OOF condition. The LCV and Frame Error
Counters continue counting errors during an OOF condition. Both counters also have ripple carry outputs
available when the PPDL port is not in use. These outputs are on the RDAT[5] and IDLE pins, respectively.
Saturation of these two counters can be disabled without enabling the respective interrupts by setting the
Disable Saturation of LCV/Frame Errors bit [DisLCV/Ferr;CR04.4] in the Feature Control Register
[CR04;0x04]. This allows external enlargement of these counters by use of the ripple carry outputs without
interruption of the microprocessor.
0x20—DS3 Parity Error Counter (SR07)
7
DS3ParCtr[7]
6
DS3ParCtr[6]
5
DS3ParCtr[5]
4
DS3ParCtr[4]
3
DS3ParCtr[3]
2
DS3ParCtr[2]
1
DS3ParCtr[1]
0
DS3ParCtr[0]
DS3ParCtr[7:0]
DS3 Parity Error Counter—Increments for each M-frame in which the calculated parity of the
received data bits of the previous M-frame do not match the received parity bits. If the two
parity bits are different this counter will increment.
100441E
Conexant
3-11