CN8330 Datasheet, PDF (53/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
2.0 Functional Description
2.4 Receiver Operation
Timing for this operation is shown in Figure 2-14.
Illustrated are cases of a good packet received, a packet received with a bad
FCS, and an aborted packet. Each packet is shown with one idle flag marking the
end of the packet and the start of the next packet. However, more than one flag
can occur in the serial stream. The output data will contain each occurrence of
idle or abort flags with a pulse on RXBCK/RXGAPCK.
Figure 2-14. PPDL Receiver Timing
RXCLK
RXBCK/
RXGAPCK
RDAT[7:0] _Data
Data
Flag
Data
IDLE/FRMCAR
Good Packet
VALFCS/
TXOVH
Packet
w/Bad FCS
IDLE/FRMCAR
VALFCS/
TXOVH
RDAT[7:0] Data
Abort
Flag
Data
Aborted
Packet
IDLE/FRMCAR
VALFCS/
TXOVH
RXBCK/RXGAPCK is generated from the falling edge of the receive serial
clock input (either DS3CKI or RXCKI depending on FIFEN) and is present
continuously like the transmit byte clock. Nominally there will be one pulse on
RXBCK/RXGAPCK for every eight clock cycles on the receive serial clock.
When an inserted transparency bit must be deleted or DS3/E3 overhead bits
skipped, the RXBCK/RXGAPCK period will be lengthened by one or more serial
clock cycles. RXBCK/RXGAPCK is present during the reception of FCS octets
and idle flags. The RDAT[7:0], IDLE/FRMCAR, and VALFCS/TXOVH outputs
are valid at least one serial clock cycle period before the rising edge of
RXBCK/RXGAPCK and are valid for at least two serial clock cycle periods after
the falling edge of RXBCK/RXGAPCK.
100441E
Conexant
2-31