CN8330 Datasheet, PDF (27/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
2.0 Functional Description
2.2 Line Interfaces
2.2 Line Interfaces
2.2.1 Transmitter Line Interface
The transmitted line signals are shown in Figure 2-2. Nine bits of a representative
output sequence are shown. Separate signal pins provide the appropriate output
signal for positive and negative pulses. The outputs are a full clock period wide
and change on positive clock transitions of the TCLKO pin. For additional
information on the TXPOS and TXNEG outputs refer to Transmitter Outputs in
the Transmitter Operation section in this chapter
B3ZS/HDB3 encoding is performed automatically on the output data stream;
however, this encoding can be disabled to send AMI data without any zero code
suppression. Transmit NRZ data, prior to B3ZS/HDB3 encoding, is also available
on the RDAT[7]/TXNRZ pin when parallel mode is not selected and on the
RXCCK/TXNRZ pin when PPDLONLY mode is selected.
Figure 2-2. Transmitter Line Driver Outputs
TCLKO
TXPOS
TXNEG
100441E
Conexant
2-5