CN8330 Datasheet, PDF (44/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

2.0 Functional Description
2.4 Receiver Operation
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
2.4 Receiver Operation
2.4.1 Bipolar-to-Unipolar Conversion
The bipolar-to-unipolar recovery circuit includes the B3ZS/HDB3 decoding
circuit. Decoding is done according to TR-TSY-000009 for B3ZS or G.703 for
HDB3. A circuit detects the B3ZS/HDB3 signature and the substitution back to
three or four zeros is made. Substitution to three or four zeros is made on every
occurrence of 00V/B0V (B3ZS) or 000V/B00V (HDB3). Bipolar and line code
violations (other than those associated with a valid B3ZS/HDB3 signature) are
counted in the 16-bit DS3/E3 LCV Counter [SR12,SR13;0x25,0x26] that is
cleared when read. In DS3 mode, a substitution pattern of improper polarity (B0V
for 00V or vice versa) will be decoded to three zeros but will be counted as a
bipolar violation. Occurrences of three or more zeros before B3ZS decoding will
also be counted as a bipolar violation.
In E3 mode, Line Code Violations (LCVs) are counted in the DS3/E3 LCV
Counter. An LCV is defined by ITU-T O.161 as two consecutive BPVs of the
same polarity. Occurrences of four or more zeros before HDB3 decoding will not
be counted as an LCV.
B3ZS/HDB3 decoding can be defeated by connecting the RXPOS and
RXNEG inputs together and supplying NRZ input data to both pins or by setting
the AMI/LCV2 control bit high and supplying a non-encoded AMI signal on
RXPOS and RXNEG.
2.4.2 Receive FIFO
The receiver circuit contains a 16-bit FIFO buffer immediately following the
B3ZS decoding circuit to provide jitter elasticity of up to ± 5 unit intervals. The
data is clocked into the FIFO buffer with the incoming DS3CKI clock. Data is
clocked out of the FIFO buffer and into the remaining receiver circuitry by the
RXCKI which is a dejittered version of DS3CKI. The FIFO buffer circuit
provides a VCO control signal to indicate the phase relationship of the FIFO
buffer input and output clocks. Both clocks are divided by 16 internally to derive
the VCO output as shown in Figure 2-10. This signal can be used to control the
clock recovery circuit producing the smoothed RXCKI. The FIFO buffer circuit is
bypassed and all receiver circuitry is clocked with DS3CKI if FIFEN is low.
RXCKI should be tied to ground if the FIFO buffer is disabled.
Figure 2-10. VCO Output Signal Timing
DS3CKI
÷ 16
RXCKI
÷ 16
VCO
Output
2-22
Conexant
100441E