CN8330 Datasheet, PDF (76/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

4.0 Mechanical/Electrical Specifications
4.1 Timing Requirements
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
Table 4-1. Microprocessor Interface Timing (2 of 2)
Symbol
Parameter
Min. Typical Max.
t_clcl
ALE Low to RD*/WR* Low
10
—
—
t_ds
Data Stable Before WR* High
25
—
—
t_dh
Data Hold after WR* High
10
—
—
t_sh
Address/Select Hold after RD*/WR* Low
110
—
—
—
Controller Port Cycle Time
154
—
—
NOTE(S):
(1) _{Tcyc = Period of clock connected to the DS3CKI pin.}
(2) _{The external address/data bus capacitance will increase the data hold time if the bus remains undriven.}
Units
ns
ns
ns
ns
ns
Figure 4-1. Microprocessor Interface Timing
CS
RD*/WR*
AD[7:0]
ALE
tadrdl
tadwrh
tsh
twrw
tas
tcale
tah
tclcl
trdd
tds
tdh
trdh
trwa
4-2
Conexant
100441E