CN8330 Datasheet, PDF (88/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

Appendix A Multimegabit HDLC Formatter
A.2 Block and Logic Diagrams
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
Figure A-2 is a logic diagram showing the functional partitioning of the pins.
This diagram pertains only to HDLC mode operation, for which some of the pins
are reassigned from CN8330 framer functions, i.e., the transmit data output
comes from a pin (RXCCK/TXNRZ) assigned to the receiver in CN8330 framer
operation.
Figure A-2. HDLC Formatter Logic Diagram
Receive Data Input I
Receive Data Input I
Receive Clock Input I
Ground I
Ground I
13 RXPOS
14 RXNEG
15 DS3CKI
16 RXCKI
11 FIFEN
Receiver
Section
RXDAT ²⁰
RXMSY ²¹
RXCLK ²²
CBITO ³⁷
TXNRZ ³⁸
RDAT[7:0] ^34-22
IDLE ²⁴
VALFCS ²⁵
VCO ¹²
RXBCK ²³
Transmit Clock Input I
Ground I
Transmit Byte Input I
Send FCS Control I
Send Message Control I
58 _TXCKI
45 _CBITI
47–50, 53–56 _TDAT[7:0]
43 _SNDFCS
42 _SNDMSG
Transmitter
Section
TXBCK 57
TXCCK 46
TXPOS 40
TXNEG 39
TXSYO 59
TCLKO 18
Address Latch Enable I
Chip Select I
Read Strobe I
Write Strobe I
Address-Data Bus I/O
67 _ALE
64 _CS
65 _RD*
66 _WR*
2–9 _AD[7:0]
Local Processor
Interface
CNTINT 62
DLINT 63
O Receive Serial Data Output
O No Connect
O Receive Clock Output
O No Connect
O Transmit Data Output
O Receive Byte Output
O Receive Idle Status
O Receive FCS Status
O No Connect
O Receive Byte Clock
O Transmit Byte Clock
O No Connect
O No Connect
O No Connect
O No Connect
O Transmit Clock Output
O _{No Connect}
O _{No Connect}
VCC I
Ground I
Ground I
Initialization Input I
44 PPDLONLY
61 MON/MIC* _{Control and}
60 TESTI
Test
19 INIT*
TESTO ⁴¹
O No Connect
I = Input, O = Output
A-4
Conexant
100441E