CN8330 Datasheet, PDF (43/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
2.0 Functional Description
2.3 Transmitter Operation
2.3.11 Test Equipment Specific Features
Additional features in the transmitter are available if parallel mode is not selected
(ParaEn = 0). The RDAT[7]/TXNRZ pin becomes an output of the transmit data
in NRZ format before being presented to the B3ZS/HDB3 encoder. The
TDAT[5]/TXENCI pin is an input directly to the B3ZS/HDB3 encoder. This input
is selected if the TstEqSel bit is set high. This allows either direct insertion of data
for B3ZS/HDB3 encoding or modification of the transmit data via RDAT[7] and
reinsertion of this stream for encoding. The TDAT[4]/LCVERRI pin is an input
that allows insertion of line code violations into the transmit data stream. This
input is also enabled when the TstEqSel bit is set high. When enabled, a line code
violation will be inserted at the next opportunity each time the LCVERRI pin is
high. The input should be high for only one clock cycle to guarantee that only one
line code violation is generated. If the AMI/LCV2 control bit in the Feature
Control Register is low, a valid insertion opportunity is defined as the second 1 in
a 11 sequence. If AMI/LCV2 is high, a valid insertion opportunity is defined as
the next B3ZS/HDB3 substitution. The opposite polarity of substitution pattern
will be inserted if an error is to be generated (a B0V/B00V instead of an
00V/000V or vice versa). This avoids the possibility of incorrectly emulating a
B3ZS/HDB3 substitution pattern and causing bit errors.
NOTE: B = Legal Bipolar Pulse; V = Bipolar Violation Pulse.
100441E
Conexant
2-21