CN8330 Datasheet, PDF (87/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
Appendix A Multimegabit HDLC Formatter
A.2 Block and Logic Diagrams
A.2 Block and Logic Diagrams
The transmit serial clock is applied to the TXCKI input of the HDLC transmitter.
The circuit generates a byte clock and either idle code, a serialized message byte,
an FCS sequence, or an abort sequence on the RXCCK/TXNRZ output pin in
response to control signal inputs. At the end of a message, the FCS is generated.
Either a 16- or 32-bit Cycle Redundancy Check (CRC) can be generated for the
FCS. A line loopback function that will loop the receive input directly to the
transmit output for end-to-end loopback is provided.
In the receive direction, serial data is taken from the receiver inputs RXPOS
and RXNEG, or, if source loopback is set, from the transmitter output. The serial
clock is connected to the DS3CKI pin on the HDLC receiver. The receiver derives
bytes of data, a byte clock, idle channel, and valid FCS indications from the
received serial data. The source loopback function can be used to provide a
diagnostic test of the HDLC transmitter and receiver.
A microprocessor interface is required to configure the circuit for HDLC
operation and to control loopbacks and FCS options for the HDLC transmitter
and receiver. The control pins consist of the read and write strobes and a chip
select signal.
100441E
Conexant
A-3