CN8330 Datasheet, PDF (89/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
Figure A-3. HDLC Formatter Logic Diagram - 80-Pin MQFP
Appendix A Multimegabit HDLC Formatter
A.2 Block and Logic Diagrams
Receive Data Input I
Receive Data Input I
Receive Clock Input I
Ground I
Ground I
5 RXPOS
6 RXNEG
7 DS3CKI
8 RXCKI
3 FIFEN
Receiver
Section
RXDAT ¹²
RXMSY ¹³
RXCLK ¹⁴
CBITO ³³
TXNRZ ³⁴
RDAT[7:0] ^22-29
IDLE ¹⁶
VALFCS ¹⁷
VCO ⁴
RXBCK ¹⁵
Transmit Clock Input I
56 _TXCKI
Ground I
42 _CBITI
Transmit Byte Input I ^{44-47, 51-54} TDAT[7:0]
Send FCS Control I
39 _SNDFCS
Send Message Control I
38 _SNDMSG
Transmitter
Section
TXBCK 55
TXCCK 43
TXPOS 36
TXNEG 35
TXSYO 57
TCLKO 10
Address Latch Enable I
Chip Select I
Read Strobe I
Write Strobe I
Address-Data Bus I/O
69 _ALE
66 _CS
67 _RD*
68 _WR*
73-80 _AD[7:0]
Local Processor
Interface
CNTINT 64
DLINT 65
O Receive Serial Data Output
O No Connect
O Receive Clock Output
O No Connect
O Transmit Data Output
O Receive Byte Output
O Receive Idle Status
O Receive FCS Status
O No Connect
O Receive Byte Clock
O Transmit Byte Clock
O No Connect
O No Connect
O No Connect
O No Connect
O Transmit Clock Output
O _{No Connect}
O _{No Connect}
VCC I
Ground I
Ground I
Initialization Input I
41 PPDLONLY
63 MON/MIC* _{Control and}
58 TESTI
Test
11 INIT*
TESTO ³⁷
O No Connect
I = Input, O = Output
100441E
Conexant
A-5