CN8330 Datasheet, PDF (31/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
Figure 2-5. Transmitter Timing for Parallel DS3 Mode
TXCKI
TXSYO
TXBCK/
TXGAPCK
TDAT[7:0]
Data
Data
Data
2.0 Functional Description
2.3 Transmitter Operation
Data
Data
Subframe 7
Subframe 1
2.3.3 E3 Mode
The clock and data edges for E3 mode have the same relationship as in DS3
mode. The synchronization overhead for E3 mode is 12 contiguous bits in each
frame rather than being distributed throughout the frame. The input bits are
synchronized to the M-frame sync signal, which can be externally provided or
internally generated from the M-frame sync signal. Serial input data must contain
bit positions for the overhead bits, although these are not used unless external
insertion is enabled. The clock frequency is nominally 34.368 MHz and the
transmit data input is sampled on the falling edge of the clock signal. The path
delay of the transmitter from the serial data input to the positive and negative line
driver outputs is seven cycles of the transmit clock. This delay includes HDB3
encoding. The delay from the serial data input to the NRZ output is two clock
cycles and the coding delay of the HDB3 encoder is five clock cycles.
The TDAT[7]/TXSYI signal should have a low-to-high transition from the last
bit of the M-frame (bit 1536) to the first bit of the FAS (bit 1). TXSYO may be
used to synchronize external circuitry. Serial data may be provided alternatively
in response to the TXBCK/TXGAPCK output without providing frame
synchronization or overhead bit slots. Figure 2-6 illustrates the timing with
propagation delays shown as negligible. Refer to the Electrical and Mechanical
Specifications chapter for actual propagation delay specifications. Note that in E3
mode gapped clock TXBCK/TXGAPCK is one clock cycle late relative to the
overhead bit positions when compared to the same relationship in DS3 mode.
This clock can still be used for data input to the transmitter. The last data bit
clocked in external circuitry by the gapped clock output should be held during the
overhead interval and will be sampled by the first falling edge of TXCKI after the
overhead interval. This bit will appear as the first bit in the information field after
the overhead field.
100441E
Conexant
2-9