CN8330 Datasheet, PDF (38/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

2.0 Functional Description
2.3 Transmitter Operation
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
The Transmit FEAC Channel Byte Register controls the byte to be transmitted
on the TxFEAC channel. All messages for transmission on this channel must be
in the form “0xxxmmm011111111". The rightmost bit of this sequence is the first
bit transmitted on the channel. To initiate transmission of a message byte in the
TxFEAC channel, the desired byte in the form 0mmmxxx0 is written into the
Transmit FEAC Channel Byte Register. Transmission of the flag (11111111) is
automatic. Each time the message is sent, an interrupt will be issued on the
DLINT/SOURCELB pin and will appear in the Data Link Interrupt Status
Register to request a new byte from the processor. The Transmit FEAC Channel
Byte Register must be written to clear the interrupt. If multiple transmissions of
the same byte are desired, the processor should rewrite the desired byte on each
interrupt and count the interrupts until the desired number of transmissions have
taken place. Interrupts from the TxFEAC channel will occur at a rate of
approximately one interrupt per 1.7 msec.
Transmit FEAC clears the internal data shift buffer after sending CR03
contents unless the host has again written to CR03. When the host writes CR03,
CN8330 transfers CR03 contents to an internal data shift buffer and then
immediately raises an interrupt (SR02.1) which tells the host that another
codeword (or the same one) can be written. After the interrupt the host must write
to CR03 within 1.7ms to keep sending codewords, else after sending the shift
buffer contents CN8330 will automatically return to sending idle (all ones) FEAC
codewords.
In summary, Transmit FEAC clears the internal data shift buffer after sending
the transmit FEAC channel byte from the CR03 register contents unless the host
has again written to this register (CR03). When the host writes to Transmit FEAC
Channel byte Register (CR03), CN8330 transfers the contents to an internal data
shift buffer and then immediately raises an interrupt in the Data Link Interrupt
Status Register (SR02.1) which tells the host that another code word (or the same
one) can be written. After the interrupt, the host must write to Transmit FEAC
Channel Byte Register (CR03) within 1.7 ms to keep sending code words, or else
after sending the shift buffer contents CN8330 will automatically return to
sending idle (all ones) FEAC codewords.
If a one is in either the MSB or LSB position of the TxFEAC field, then
continuous transmission of idle flags is enabled and no interrupts will be issued
until a byte of the proper format is written to the Transmit FEAC Channel Byte
Register.
Interrupts from the TxFEAC channel transmitter will appear on Transmit
FEAC Channel Interrupt bit. Interrupts must be enabled to appear on
DLINT/SOURCELB by setting the CBitP/DL bit in the Mode Control Register.
2.3.8 PPDL Transmitter
The payload portion of the CN8330 data stream can come from an internal PPDL
formatter that provides an external byte-wide data interface and a byte clock. This
source is enabled by setting the ParaEn bit in the Feature Control Register. The
PPDL formatter is controlled by signals applied on the SNDMSG and SNDFCS
pins. Both byte-wide and nibble-wide inputs can be provided. Optional HDLC
formatting with 16-bit or 32-bit FCSs is provided.
2-16
Conexant
100441E