CN8330 Datasheet, PDF (26/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

2.0 Functional Description
2.1 Overview
2.1.3.2 Microprocessor
Interrupts
2.1.3.3 Address Map
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
There are two separate interrupt pins that can be connected to the microprocessor
(or microcontroller): Counter and Data Link. The counter interrupt pin
(CNTINT/LINELB) combines seven sources of interrupts on an external pin
connected to the microprocessor. This interrupt signal is active low and is a
composite indication of all interrupt sources that are enabled in the Status
Interrupt Control Register [CR02;0x02]. The interrupt source can be determined
by reading the Counter Interrupt Status Register [SR01;0x11]. The data link
interrupt pin (DLINT/SOURCELB) is a composite indication of the interrupts
from four sources. The interrupt source can be determined by reading the Data
Link Interrupt Status Register [SR02;0x12]. When the C-Bit Parity Mode/Enable
DLINT bit [CBitP/DL;CR00.0] is not set, the DLINT/SOURCELB pin is held
high (inactive). The two interrupt pins are open-drain outputs and can be
connected to form a single-wire ORed interrupt, if desired.
The register address map for the CN8330 is given in Table 3-1 through Table 3-4,
Register Summary. There are three types of registers: Control Registers, which
can be read or written; Status Registers and Counters which can only be read; and
Data Link Message Buffers which can be read or written. The Control Registers
serve as latches that are modified by a microprocessor write operation and can
also be read to verify contents. They are located at addresses 0x00–0x05. Status
Registers are located at addresses 0x10–0x16. Maintenance Error Counters are
located at addresses 0x20–0x26. The Transmit Terminal Data Link Message
Buffers are located at addresses 0x30–0x37, and the Receive Terminal Data Link
Message Buffers are located at addresses 0x40–0x47. The chip select input
(CS/ALM0) must be high to address the CN8330 and to enable read or write
operations.
2-4
Conexant
100441E