CN8330 Datasheet, PDF (20/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

1.0 Product Description
1.1 Pin Descriptions
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
Table 1-2. Hardware Signal Definitions (3 of 5)
Pin Label
Signal Name
I/O
Definition
TCLKO
Transmit Clock Out
O Used to clock out the TXPOS and TXNEG outputs.
Data is clocked out on the rising edge of TCLKO.
TXPOS, TXNEG
TDAT[3:0]
Transmit Bipolar
Positive, Negative
Transmit Data Bits 3–0 (Bit 0
is the LSB)
O The positive and negative pulses generated by the
B3ZS/HDB3 encoder.
I
In parallel mode⁽²⁾, these bits form the lower nibble
of the byte-oriented data that is input to the PPDL
transmitter in response to the transmit byte clock,
TXBCK.
TDAT[4]/LCVERRI
Transmit Data Bit 4/Line
Code Violation Error In
I In parallel mode, the TDAT[4] is bit 4 of the
byte-oriented data that is input to the PPDL
transmitter. In serial mode, LCVERRI allows test
equipment to insert LCVs into the transmit stream
under microprocessor control, in both DS3 and E3
modes.
TDAT[5]/TXENCI
Transmit Data Bit 5/Transmit
Encoder In
I In parallel mode, TDAT[5] is bit 5 of the
byte-oriented data that is input to the PPDL
transmitter. In serial mode, TXENCI is an alternate
direct input to the B3ZS/HDB3 encoder.
TDAT[6]/TXDATI
Transmit Data Bit 6/Transmit
Serial Data
I In parallel mode, TDAT[6] is bit 6 of the
byte-oriented data that is input to the PPDL
transmitter. In serial mode, TXDATI is applied to the
transmitter.
TDAT[7]/TXSYI
Transmit Data Bit 7/Transmit
M-Sync In
I In parallel mode, TDAT[7] is the MSB (Bit 7)of the
byte-oriented data that is input to the PPDL
transmitter. In serial mode, TXSYI is applied to the
transmitter.
TXSYO
Transmit M-Sync Out
O The transmit M-frame sync output.
TXCKI
Transmit Clock In
I TXCKI rising edge is used to sample parallel data,
while the falling edge is used to sample serial data.
TXBCK/TXGAPCK
Transmit Byte Clock/Gapped
Clock
O In parallel mode, TXBCK clocks the byte-oriented
data that is input to the PPDL transmitter. In serial
mode, TXGAPCK is a transmit clock that is gapped
during overhead bit intervals in either E3 or DS3
modes.
SNDMSG
Send Message
I In parallel mode, SNDMSG initiates message
transmission in the PPDL transmitter.
SNDFCS
Send Frame Check Sequence
I
In parallel mode, SNDFCS initiates transmission of
the 16- or 32-bit frame check sequence on the PPDC
transmitter.
CBITI
Transmit C/N-Bit Serial In
I The serial C-bit (DS3 mode) or N-bit (E3 mode) data
input to be transmitted.
TXCCK
Transmit C/N-Bit Clock
O Used to sample the CBITI input on the falling edge of
TXCCK.
PPDLONLY
Payload Parallel Data Only
Select
I Enables the PPDL-only mode in which no DS3/E3
framing is inserted. This mode is entered by tying
this pin high.
1-10
Conexant
100441E