CN8330 Datasheet, PDF (19/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
Table 1-2. Hardware Signal Definitions (2 of 5)
Pin Label
Signal Name
AD[4]/IDLE
Address-Data 4/Idle Code
Detection
AD[5]/PAR
Address-Data 5/Parity Error
Detection
AD[6]/LCV
Address-Data 6/Line Code
Violation
AD[7]/FRMERR
Address-Data 7/
Frame Bit Error
CNTINT/LINELB
Counter Interrupt/
Line Loopback
DLINT/SOURCELB
Data Link Interrupt/Source
Loopback
TESTI
INIT*
Test In
Initialization
TESTO
Test Out
1.0 Product Description
1.1 Pin Descriptions
I/O
Definition
B/O Part of the bidirectional 8-bit multiplexed
address-data bus when MON/MIC* is tied low. When
in stand-alone mode, this pin is an active-high
monitor output indicating an idle code detection.⁽¹⁾
B/O Part of the bidirectional 8-bit multiplexed
address-data bus when MON/MIC* is tied low. When
in stand-alone mode, this pin is an active-high
monitor output indicating a parity error.⁽¹⁾
B/O Part of the bidirectional 8-bit multiplexed
address-data bus when MON/MIC* is tied low. When
in stand-alone mode, this pin is an active-high
monitor output indicating a line code violation.⁽¹⁾
B/O Part of the bidirectional 8-bit multiplexed
address-data bus when MON/MIC* is tied low. When
in stand-alone mode, this pin is an active-high
monitor output indicating a frame bit error.⁽¹⁾
O/I The composite interrupt signal generated by the
error counters when MON/MIC* is tied low. When
MON/MIC* is tied high, this pin controls line
loopback transmission in stand-alone mode. CNTINT
is an active-low output; LINELB is an active-high
input.
O/I The composite interrupt signal generated by the data
links when MON/MIC* is tied low. When MON/MIC*
is tied high, this pin controls source loopback
transmission in stand-alone mode. DLINT is an
active-low output; SOURCELB is an active-high
input.
I Used for test functions only. Should be tied to
ground for normal operation.
I Active low initialization control. Not all internal
storage elements are affected by this signal. See
Clock Interface and Initialization in the Overview
section of the Functional Description chapter.
O Used for test functions only. Should be left
disconnected for normal operation.
100441E
Conexant
1-9