CN8330 Datasheet, PDF (46/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

2.0 Functional Description
2.4 Receiver Operation
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
Figure 2-12 illustrates the receiver timing for the parallel DS3 mode. This
mode is enabled by setting the ParaEn bit in the Feature Control Register and
setting the DisPPDL bit in the PPDL Control Register. The receive data is valid
on either the rising or falling edge of RXBCK.
Figure 2-12. Receiver Timing for Parallel DS3 Mode
RXCLK
RXMSY
RXBCK/
RXGAPCK
RDAT[7:0]
data
data
data
data
data
Subframe 7
Subframe 1
Figure 2-13 illustrates a timing diagram for the E3 receiver output signal with
the PPDL enabled. The clock and data edge relationships are similar to those in
DS3 mode. The M-frame synchronization signal RXMSY is high during the
12-bit block corresponding to the 10-bit FAS and the A and N bits. If the PPDL is
enabled, the M-frame synchronization signal will be high for four additional bit
periods corresponding to the 1100 pattern found in SMDS formatted signals.
RDAT[6]/RXOVH will be low for 12 bits in serial mode and for 16 bits if the
PPDL is enabled.
Figure 2-13. E3 Receiver Output Timing
RXCLK
RXDAT
1520/1524 Info Bits
RDAT[6]/
RXOVH
RXBCK/
RXGAPCK
RXMSY
10-Bit FAS
A/N/1100
Info Bits
Low for 12 or 16 Bits
High for 12 or 16 Bits
2-24
Conexant
100441E