CN8330 Datasheet, PDF (56/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

2.0 Functional Description
2.5 Monitor Mode for Stand-Alone Operation
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
2.5 Monitor Mode for Stand-Alone Operation
Operation without a microprocessor is possible with the MON/MIC* pin tied
high. In this mode of operation, the transmitter is set to M13 format with External
C-Bit Insert [ExtCBit;CR00.2] enabled. E3 mode operation is not available
without a microprocessor. External circuitry must format all of the C-bit locations
to the desired values and present them on the CBITI pin in response to the
TXCCK clock output. Proper C-bit ordering can be determined by the
relationship to the input or output M-frame syncs (TDAT[7]/TXSYI or TXSYO).
The parallel data input port for the PPDL transmitter is enabled by setting the
PAREN input high. Setting the CRC32 input high selects the 32-bit CRC mode.
Two special modes are available when in stand-alone operation. When the
PAREN input is high and the PPDLONLY input is low, the byte-wide interfaces
are enabled with transparency bit insertion/deletion disabled. This allows the
CN8330 to be used as a DS3 device with a parallel interface. When the PAREN
input is high and the PPDLONLY input is high, the byte-wide interfaces are
enabled. Transparency bit insertion/deletion is enabled. DS3 framing is disabled.
This allows the CN8330 to be used as a high-speed HDLC formatter. The
transmit serial data stream is available in NRZ format on the RXCCK pin in this
mode.
Alarm generation in this mode is controlled by the CS/ALM0 and RD*/ALM1
pins. Setting these pins, as described under Mode Control Register in the
Registers chapter of this document, will enable transmission of the specified
alarm signal (the TxAlm[1:0] bits work identically to the pins).
The receiver will monitor all DS3 maintenance alarms and indications and
provide occurrences of any alarm on the FRMERR, LCV, PAR, IDLE, YEL, AIS,
OOF, and LOS pins (AD[6:0]). These indications can then be counted by external
circuitry for appropriate action. The received data is present on the RXDAT pin
and, if the parallel port is enabled, on the RDAT[7:0] pins. All C-bits are clocked
out on CBITO for external processing.
2-34
Conexant
100441E