CN8330 Datasheet, PDF (42/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

2.0 Functional Description
2.3 Transmitter Operation
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
FCS calculation can be limited to the first N bytes of the transmitted message
by setting the Limit Frame Check Sequence Calculation [LimitFCS;CR05.3]
control bit. In this mode, the FCS is calculated on the first N bytes transmitted
after the opening flag and then held until the end of the message. It is then
appended to the end of the message in normal fashion. The desired number N can
be from 1 to 16 (a value of 0 gives N=16) and is loaded in the Frame Check
Sequence Calculation Count [FCSCnt[3:0];CR05.7:4] control field. This allows
FCS calculation only on the header information in a T1 packet voice format.
2.3.9 PPDLONLY Mode
The transmitter can be placed in a mode where the entire transmit stream consists
of data with no DS3/E3 overhead bits inserted. This mode is enabled by providing
a high input on the PPDLONLY input pin. This mode allows the CN8330 to be
used as a high-speed PPDL formatter and can be used at any clock rate up to the
full 52 MHz capability of the device. Data and controls are provided to the
transmitter in response to the transmit byte clock. When PPDLONLY mode is set,
the transmit NRZ data stream is available on the RXCCK/TXNRZ pin.
2.3.10 Transmitter Outputs
The TXPOS and TXNEG pins provide a variety of signals depending on the
control bits in the Feature Control Register. Table 2-1 summarizes the available
output combinations when the Test Equipment Feature Select bit
[TstEqSel;CR04.7] is low.
Table 2-1. Transmit Encoding Options
DisEnc
AMI/LCV2
Transmit Output
0
0
B3ZS/HDB3 Encoded Data on TXPOS, TXNEG
0
1
AMI Encoded Data on TXPOS, TXNEG
1
0
NRZ Data on TXPOS, Transmit Clock on TXNEG
1
1
NRZ Data on TXPOS, Transmit Clock on TXNEG
2-20
Conexant
100441E