CN8330 Datasheet, PDF (75/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

4
4.0 Mechanical/Electrical Specifications
4.1 Timing Requirements
Table 4-1 and Figure 4-1 illustrate the timing requirements for the microprocessor
interface. The parameter t_cyc is the period of the receive DS3/E3 clock (DS3CKI).
This clock signal is used in the read circuit of the microprocessor to ensuring no
status events are missed and that counter values are accurately read.
Read operation requires the read strobe to be low for three t_cyc clock cycles
ensuring that changing status and error counts are properly processed. If a gapped
clock is applied to the circuit, it is sufficient to allow three receive clock cycles
between read strobes to allow a latching circuit to clear in the microprocessor
interface.
Table 4-1. Microprocessor Interface Timing (1 of 2)
Symbol
Parameter
t_as
Address Setup before ALE Low
t_cale
Controller ALE Pulse Width
t_ah
Address Hold after ALE Low
t_rwa
RD*/WR* High to ALE High
t_adwrh
Address/Select to WR* High
t_adrdl
Address/Select to RD* Low
t_wrw (Read Operation) _{RD* Pulse Width}⁽¹⁾
t_wrw (Write Operation) WR* Pulse Width
t_rdd
RD* Low to Data Available
t_rdh
Read Data Hold Time⁽²⁾
Min.
7
34
10
10
117
17
3 × tcyc
100
—
3
Typical
—
—
—
—
—
—
—
—
—
—
Max.
—
—
—
—
—
—
—
—
30
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100441E
Conexant
4-1