CN8330 Datasheet, PDF (22/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

1.0 Product Description
1.1 Pin Descriptions
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
Table 1-2. Hardware Signal Definitions (5 of 5)
Pin Label
Signal Name
I/O
Definition
RDAT[3]/IDLE
Receive Data Byte 3/Idle
Code Detection
RDAT[4]/
FRMERR
Receive Data Byte 4/Frame
Error Detection
RDAT[5]/
LCVCAR
Receive Data Byte 5/Line
Code Violation Carry
RDAT[6]/RXOVH
Receive Data Byte 6/Receive
Overhead Detection
RDAT[7]/TXNRZ
Receive Data Byte 7/ Trans-
mit NRZ Out
IDLE/
FRMCAR
Idle/Frame Carry
VALFCS/TXOVH
Valid FCS Received/Transmit
Overhead
VCO
Voltage-Controlled Oscillator
Output
V_DD
Supply Voltage
GND
Ground
O Part of the 8-bit data bus output from the PPDL
receiver when parallel mode is enabled. When
parallel mode is disabled, this pin is an active-high
monitor output indicating idle code detection.
O Part of the 8-bit data bus output from the PPDL
receiver when parallel mode is enabled. When
parallel mode is disabled, this pin is an active-high
monitor output indicating frame error detection.
O Part of the 8-bit data bus output from the PPDL
receiver when parallel mode is enabled. When
parallel mode is disabled, this pin is an active-high
ripple carry output from the LCV error counter.
O Part of the 8-bit data bus output from the PPDL
receiver when parallel mode is enabled. When
parallel mode is disabled, this pin is an active-low
monitor output indicating the receive overhead bit
positions.
O Part of the 8-bit data bus output from the PPDL
receiver when parallel mode is enabled. When
parallel mode is disabled, this pin is a monitor
output for the transmit NRZ data.
O Set if an idle flag is received after a non-idle
sequence, when parallel mode is enabled. When
parallel mode is disabled, this pin is an active-high
ripple carry output from the frame error counter.
O Active high if a valid FCS was received, when parallel
mode is enabled. When parallel mode is disabled,
this pin is an active-low transmit overhead bit
position indicator.
O Used as the phase control for the clock recovery
circuit that generates the dejittered clock, RXCKI.
Valid only when FIFEN is high. FIFEN enables the
internal FIFO when tied high.
Four pins are provided for power.
Five pins are provided for ground.
NC
Not Connected
These pins are not connected internally.
NOTE(S):
(1) _{Standalone operation is valid only in DS3 mode.}
(2) _{Parallel mode is enabled by setting the Parallel Data Enable bit [ParaEn;CR04.3] in the Feature Control Register [CR04; 0x04]}
when MON/MIC* is low. When MON/MIC* is high, Parallel mode is entered by tying the ALE/PAREN pin high.
1-12
Conexant
100441E