CN8330 Datasheet, PDF (48/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

2.0 Functional Description
2.4 Receiver Operation
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
The frame bits are monitored to determine errors and OOF conditions. The
OOF indicator is set whenever 3 of 16 consecutive F framing bits are in error or
when 2 of 3 consecutive M-frames have M-bit errors in DS3 mode. In E3 mode,
four consecutive occurrences of an incorrect FAS will result in an OOF condition.
Auxiliary error indication outputs are available when the PPDL is not enabled. A
1-bit-period-wide pulse for each F- or M-bit error or each incorrect FAS is
available on the RDAT[4]/FRMERR pin. Indications of LOS, OOF, AIS, and
IDLE are available on RDAT[0:3], respectively. These indications are not
internally latched and do not require action from the microprocessor to clear.
2.4.6 Terminal Data Link Reception
LAPD receiver logic for the terminal data link in C-bit parity format is included
in the framer circuit. Data link reception is also provided for the N-bit in E3
mode. This logic manages an 8-byte message buffer for the data link receiver. Idle
and abort flag detection, FCS checking, and stuffed zero removal are also
included. Microprocessor interrupts are used to synchronize the passing of data to
and from the message buffer.
The terminal data link receiver is under the control of the received data stream
only. The receiver interrupt is under the control of Receive Data Link Interrupt
Enable [RxTDLIE;CR01.7] in the Terminal Data Link Control Register and
CBitP/DL in the Mode Control Register. This interrupt must be enabled by setting
both of these bits for receiver interrupts to appear on the DLINT/SOURCELB
output and for proper interaction with the processor. The C-bits in subframe 5 in
C-bit parity mode or standard DS3 mode (the N-bit in E3 mode) are provided to
the receiver circuitry at all times. Therefore, when the DS3/E3 Maintenance
Status Register indicates that alarms are being received rendering the data link
information useless, it may be desirable to disable the RxTDLIE bit to prevent
excessive or spurious interrupts to the processor. Receiver status is monitored via
Receive Terminal Data Link Interrupt [RxTDLItr;SR02.2] in the Data Link
Interrupt Status Register and via the Terminal Data Link Status Register
[SR04;0x14]. When a receive data link interrupt is generated on
DLINT/SOURCELB, the RXTDLItr bit will be set in the Data Link Interrupt
Status Register. If this bit is observed upon reading the Data Link Interrupt Status
Register, then the Terminal Data Link Status Register should be read to get the
receiver status that caused the interrupt.
The Terminal Data Link Status Register contains 3 status bits and a 3-bit
buffer pointer. The status bits are Abort Flag Received [RxAbort;SR04.0], Bad
FCS [BadFCS;SR04.1], and Idle Code Received [RxIdle;SR04.2]. The 3-bit
buffer pointer, Byte Received [RxByte[2:0];SR04.5:3], is used to point to
locations in the 8-byte Receive Terminal Data Link Message Buffer
[RxTDL;0x40–0x47]. The buffer pointer indicates the last location written by the
data link receiver.
The receiver implements a LAPD data link per CCITT standard Q.921. The
functions provided by the data link receiver circuitry are transparency zero
removal, FCS checking, idle flag reception, and abort flag reception. There are no
restrictions on the total length of the message. Q.921 requires all messages be an
integral number of 8-bit bytes. If the receiver receives a message that is not an
integral number of bytes, the receiver status will indicate a message received with
bad FCS. The per-byte reception time is approximately 284 microseconds in C-bit
parity mode and approximately 357 microseconds in E3 mode.
2-26
Conexant
100441E