CN8330 Datasheet, PDF (50/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

2.0 Functional Description
2.4 Receiver Operation
2.4.6.1 Receiver
Interrupts
2.4.6.2 Receiver
Response Example
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
The data link receiver generates an interrupt in response to three events: the
current half of the message buffer is full, the end-of-message flag was detected, or
an abort flag was detected. The Terminal Data Link Status Register indicates the
cause of the interrupt. The interrupt will be cleared upon the reading of this
register.
If the interrupt is due to the current half of the receive buffer being full, RxIdle
will be cleared, and RxByte[2:0] will indicate which half of the buffer must be
read.
If the interrupt is due to the end-of-message flag being detected, RxIdle will
be set, BadFCS will indicate the result of the FCS error check, and RxByte[2:0]
will indicate the last location written. The processor will not be interrupted again
until 4 bytes of a new message have been received.
If the interrupt is due to an abort flag being received, Abort will be set, and
there is nothing to do other than discard any previously received message bytes.
The processor will not be interrupted again until 4 bytes of a new message have
been received.
Interrupts from the terminal data link receiver will appear on RxTDLItr in the
Data Link Interrupt Status Register. Interrupts must be enabled to appear on
DLINT/SOURCELB by setting the CBitP/DL bit in the Mode Control Register
and RxTDLIE bit in the Terminal Data Link Control Register in either C-bit
parity mode or E3 mode.
The following example shows the sequence necessary to receive an 8-byte hex
message that is stored starting in the lower half of the receive buffer. The final
interrupt indicates that two more bytes are present in the buffer but these bytes are
FCS bytes, not message bytes. When an interrupt is received, the processor reads
the Data Link Interrupt Status Register to determine the source of the interrupt. If
the source is determined to be the receive terminal data link, the processor will
respond in the following manner:
At RX Interrupt:
read address 0x14 to get status (status = 0x18: RxByte[2:0] = 011, RxIdle = 0)
read address 0x40 to get 1st data byte
read address 0x41 to get 2nd data byte
read address 0x42 to get 3rd data byte
read address 0x43 to get 4th data byte
At RX Interrupt:
read address 0x14 to get status (status = 0x38: RxByte[2:0] = 111,
RxIdle = 0)
read address 0x44 to get 5th data byte
read address 0x45 to get 6th data byte
read address 0x46 to get 7th data byte
read address 0x47 to get 8th data byte
At RX Interrupt:
read address 0x14 to get status (status = 0x0C or 0x0E: RxByte[2:0] = 001,
RxIdle = 1, BadFCS = 0 or 1)
read address 0x40 if desired (FCS byte 1)
read address 0x41 if desired (FCS byte 2)
2-28
Conexant
100441E