CN8330 Datasheet, PDF (40/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

2.0 Functional Description
2.3 Transmitter Operation
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
TXBCK/TXGAPCK is generated from TXCKI and has a duty cycle of 25
percent. TXBCK will nominally be one-eighth the TXCKI frequency but is
influenced by HDLC transparency bit insertions and DS3/E3 overhead bits. In the
absence of any transparency bit insertions or overhead bits, there will be one
pulse on TXBCK for every eight clock cycles of the TXCKI input. When a
transparency bit is inserted into the serial transmit data stream, the TXBCK
period will be lengthened to nine clock cycles of TXCKI (or up to 11 cycles if
two transparency bit insertions and a DS3 overhead bit land in the same data octet
interval). TXBCK/TXGAPCK is present continuously even during the
transmission of idle flags. The actual setup times on TDAT[7:0], SNDMSG, and
SNDFCS relative to the rising edge of TXBCK are negative. Therefore, it is
possible to read data and control from a RAM or FIFO buffer with the rising edge.
The CN8330 will sample the data after the falling edge. This allows FIFOs or
RAMs with access times of 35–40 nsec to be used.
The parallel interface can be used without transparency bit insertion by setting
the DisPPDL bit in the PPDL Control Register to a 1. In this mode, SNDMSG is
held high and SNDFCS is held low so that no flags or FCS bytes are transmitted.
Byte synchronization in the transmitter and receiver is achieved from the
M-frame sync alignment. This allows the byte-wide interface to be used as the
data input for non-HDLC payloads rather than the serial input pin. Data is
inserted on the TDAT[7:0] pins in response to TXBCK/TXGAPCK just as in the
HDLC mode. Data bytes are transmitted LSB first. If E3 mode is enabled, the
transmitted bytes are byte aligned after the 16 overhead bits for a total of 190
bytes per frame. To accommodate E3 SMDS applications, the input bytes should
be applied to the TDAT[7:0] pins in reverse bit order so that the MSB will be
transmitted first.
2-18
Conexant
100441E