CN8330 Datasheet, PDF (24/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

2.0 Functional Description
2.1 Overview
Figure 2-1. Functional Block Diagram
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
RXPOS
RXNEG
DS3CKI
TXPOS
TXNEG
TXCKI
MUX
Receive
Unipolar
Conversion
CLK
DATA
FIFO
Buffer
SOURCELB
RXCKI
FIFEN
Control
Interrupts
Address/Data
Receive Clock
and Data
Microprocessor
Interface
Control Status
CBITI
TXCCK
TXSYO
TXNRZ Data
FIFO Data
for Line
Loopback
TXPOS
TXNEG
TCLKO
Transmit
Framing and
Overhead Bit
Insertion
MUX
TXDATI
TXCKI
TXSYI
TXENCI
LINELB
Bipolar
Encoding
Test
Equipment
Feature
Select
MUX
RXPOS
RXNEG
DS3CKI
LINELB
PPDL
Receiver
Rx Timing
FEAC
Channel
Terminal
Data Link
Receiver
Frame/
Overhead
Bit Check
Frame
Recovery
Payload
Bit Check
PPDL
Transmitter
FEAC
Channel
Terminal Data
Link
Generator
Payload Bit
Pattern Insert
FEBE
Generation
LOS, LCV
VCO
RXDAT, RXCLK
RXBCK
RDAT[7:0]
Status: IDLE
VALFCS
Receive Byte
Message Buffer
Status: OOF
Frame Error
Parity
Path Parity
FEBE
X Bit
Format
RXMSY
Gapped Clock
CBITO,RXCCK
Status: AIS
IDLE
TXBCK
TDAT[7:0]
SNDMSG, SNDFCS
Transmit Byte
Message Buffer
2-2
Conexant
100441E