CN8330 Datasheet, PDF (51/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
2.0 Functional Description
2.4 Receiver Operation
2.4.7 RxFEAC Channel Reception
Receiver logic is provided for reception of the Receive Far End Alarm and
Control (RxFEAC) Channel which is present in C-bit parity mode. This channel
uses a bit-oriented protocol and received data is provided in the Receive FEAC
Channel Byte Register [SR03;0x13].
The RxFEAC channel receiver is under control only of the received data
stream. The receiver interrupt is under control of Receive FEAC Interrupt Enable
[RxFEACIE;CR02.6] in the Status Interrupt Control Register and the CBitP/DL
bit in the Mode Control Register. This interrupt must be enabled by setting both
of these bits for receiver interrupts to appear on the DLINT/SOURCELB output
and for proper interaction with the processor. The last C-bit in subframe 1 in C-bit
parity mode or in M13 mode is provided to the receiver circuitry at all times.
There is no RxFEAC channel capability in E3 mode. Therefore, when E3 mode is
selected with CBitP/DL set or when the Mode Control Register indicates that
alarms are being received rendering the data link information useless, it may be
desirable to disable the receive FEAC interrupt via the RxFEACIE bit to prevent
excessive or spurious interrupts to the processor.
Receiver status is monitored via the Receive FEAC Channel Interrupt
[RxFEACItr;SR02.0]. When an RxFEAC channel interrupt is generated on
DLINT/SOURCELB, the RxFEACItr bit will be set in the Data Link Interrupt
Status Register. If this bit is observed to be a 1 upon reading the Data Link
Interrupt Status Register, then another byte has been received and placed in the
Receive FEAC Channel Byte Register.
An idle message is all-ones and all other messages are of the form
“0xxxmmm011111111” with reception of the rightmost bit first from the
channel. The receiver logic recognizes the eight ones message flag followed by a
message byte and interrupts the controller upon reception of a valid message byte.
The “0mmmxxx0” message byte that was received is stored in the Receive FEAC
Channel Byte Register. Continuous incoming messages on the RxFEAC channel
will produce an interrupt rate of approximately one interrupt per 1.7 msec for this
interrupt source. No interrupts are generated if the RxFEAC channel is receiving
continuous idle flags, the interrupt is not enabled in the Status Interrupt Control
Register, or CBitP/DL bit is not set. Reading the Receive FEAC Channel Byte
Register clears the interrupt.
Interrupts from the RxFEAC channel receiver will appear on the RxFEACItr.
Interrupts must be enabled to appear on DLINT/SOURCELB by setting both
CBitP/DL in the Mode Control Register and the RxFEACIE bit in the Status
Interrupt Control Register.
100441E
Conexant
2-29