CN8330 Datasheet, PDF (66/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

3.0 Registers
3.2 Status Registers
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
0x12—Data Link Interrupt Status Register (SR02)
The Data Link Interrupt Status Register contains information about active data link interrupts needing service
from the controller. The controller determines the source of the data link interrupt by reading this register. The
interrupt indications are active high and can be from four sources: Transmit FEAC Channel, Receive FEAC
Channel, Transmit Terminal Data Link, and Receive Terminal Data Link. Servicing an interrupt clears the
indication in this register.
NOTE(S): Rsvd bits in Control Registers must be set to zero.
7
Rsvd
TxTDLItr
RxTDLItr
TxFEACItr
RxFEACItr
6
Rsvd
5
Rsvd
4
Rsvd
3
TxTDLItr
2
RxTDLItr
1
TxFEACItr
0
RxFEACltr
Transmit Terminal Data Link Interrupt—Set high when the transmitter has latched the present
set of controls in the Terminal Data Link Control Register [CR01; 0x01] and is ready for a new
set. Writing the Terminal Data Link Control Register clears this interrupt.
Receive Terminal Data Link Interrupt—Set high by the Receive Data Link circuitry. Reading
the Terminal Data Link Status Register clears this interrupt.
Transmit FEAC Channel Interrupt—Set high indicating that the transmitter is ready for a new
byte to be written to the Transmit FEAC Channel Byte Register. Writing the Transmit FEAC
Channel Byte clears this interrupt.
Receive FEAC Channel Interrupt—Set high when a FEAC message byte has been received
and placed in the Receive FEAC Channel Byte Register. Reading the Receive FEAC Channel
Byte Register clears this interrupt.
0x13—Receive FEAC Channel Byte (SR03)
7
RxFEAC[7]
RxFEAC[7:0]
6
RxFEAC[6]
5
RxFEAC[5]
4
RxFEAC[4]
3
RxFEAC[3]
2
RxFEAC[2]
1
RxFEAC[1]
0
RxFEAC[0]
Receive FEAC Channel Message Byte—If the incoming format is C-bit parity, this register
contains the received byte from the bit-oriented receive FEAC channel. The receive FEAC
channel is only defined in C-bit parity format. Receive FEAC message reception is described
in RxFEAC Channel Reception in the Receiver Operation section of the Functional
Description chapter. This byte is meaningless in E3 mode and should be ignored.
3-8
Conexant
100441E