CN8330 Datasheet, PDF (32/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

2.0 Functional Description
2.3 Transmitter Operation
Figure 2-6. Transmitter Timing for Serial E3 Mode
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
TXCKI
VALFCS/
TXOVH
TXBCK/
TXGAPCK
Low for 12 Bits (FAS,A,N)
TXSYO
High for 12 Bits (FAS,A,N)
TDAT[6]/TXDATI
(Serial In)
1520/1524 Info Bits
10-Bit FAS
A/N/1100
Info
TDAT[7]/TXSYI
(Sync In)
2.3.4 Framing Bit Generation
In DS3 mode, all F and M framing bits are automatically generated by the
transmitter circuitry. Additionally, the transmitter calculates the parity of each
M-frame and inserts this data into bits P1 and P2 of the following M-frame. Bits
X1 and X2 contain ones unless the Transmit Alarm Control 0 bit [TxAlm0;
CR00.4] in the Mode Control Register [CR00;0x00] is set. If set, bits X1 and X2
contain zeros. If C-bit parity mode is selected, all C-bit positions are generated
automatically by the transmitter if the External C-Bit Insert bit [ExtCBit;CR00.2]
is low. If high, all C-bits are generated internally except for the CP (subframe 3)
an FEBE (subframe 4) bit positions. These bits must be provided on the CBITI
pin at the proper time in response to TXCCK as shown in Figure 2-7. The CBITI
data must be valid on the falling edge of TXCCK. This allows the chip to be used
in a repeater mode with pass-through of the path parity and FEBE information. If
C-bit parity mode is not selected, all C-bit positions come from either the serial
data stream or the CBITI pin depending on the ExtCBit setting in the Mode
Control Register. The X, P, M, and F bit positions may be inserted from the
transmit serial data stream by setting External Overhead Insert bit
[ExtOvh;CR00.3] high.
2-10
Conexant
100441E