CN8330 Datasheet, PDF (17/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
Figure 1-4. CN8330 Framer Functional Logic Diagram - 80-Pin MQFP
1.0 Product Description
1.1 Pin Descriptions
Rx Bipolar Pos I 5
Rx Bipolar Neg I 6
Rx Line Clock In I 7
Dejittered Clock In I 8
FIFO Enable I 3
RXPOS
RXNEG
DS3CKI
RXCKI
FIFEN
Receiver
Section
RXDAT
RXMSY
RXCLK
CBITO
RXCCK/TXNRZ
RDAT[7]/TXNRZ
12 O Rx Serial Data
13 O Rx M-Sync
14 O Rx Clock
33 O Rx C/N Bit Serial Out
34 O Rx C/N-Bit Clock Out/TxNRZ
29 O Rx Data Bit MSB/TxNRZ
RDAT[6]/RXOVH 28 O Rx Data Bit 6/RX Overhead
Tx Clock In I ⁵⁶
Tx C/N Bit Serial In I ⁴²
Tx Data Bit MSB/Tx M-Sync In I ⁵⁴
Tx Data Bit 6/Tx Serial Data In I ⁵³
Tx Data Bit 5/Tx Encoder In I ⁵²
Tx Data Bit 4/LCV Error In I ⁵¹
Tx Data Bit 3 I ⁴⁷
Tx Data Bit 2 I ⁴⁶
Tx Data Bit 1 I ⁴⁵
Tx Data Bit LSB I ⁴⁴
TXCKI
CBITI
TDAT[7]/TXSYI
TDAT[6]/TXDATI
TDAT[5]/TXENCI
TDAT[4]/LCVERRI
TDAT[3]
TDAT[2]
TDAT[1]
TDAT[0]
RDAT[5]/LCVCAR
RDAT[4]/FRMERR
RDAT[3]/IDLE
RDAT[2]/AIS
RDAT[1]/OOF
RDAT[0]/LOS
IDLE/FRMCAR
VALFCS/TXOVH
VCO
RXBCK/RXGAPCK
27 O Rx Data Bit 5/ Line Code Violation Carry
26 O Rx Data Bit 4/Frame Bit Error
25 O Rx Data Bit 3/Idle Code Detection
24 O Rx Data Bit 2/Alarm Indication Signal
23 O Rx Data Bit 1/Out of Frame
22 O Rx Data Bit LSB/Loss of Signal
16 O Idle Data Rcvd/Frame Carry
17 O Valid FCS Rcvd/TX Overhead
4 O Voltage-Controlled Oscillator Output
15 O Rx Byte Clock/Gapped Clock
Send FCS I ³⁹ SNDFCS
Send Message I ³⁸ SNDMSG
Parallel Data Only Select I ⁴¹ PPDLONLY
Test In I ⁵⁸ TESTI
Initialization I ¹¹ INIT*
TXBCK/TXGAPCK
TXCCK
Transmitter _TXPOS
Section _TXNEG
TXSYO
TCLKO
55 O Tx Byte Clock/Gapped Clock
43 O Tx C/N Bit Clock
36 O Tx Bipolar Pos
35 O Tx Bipolar Neg
57 O Tx M-Sync Out
10 O Tx Clock Out
Address-Data 0/Loss of Signal B/O 80
Address-Data 1/Out of Frame B/O 79
Address-Data 2/Alarm Indication Signal B/O 78
Address-Data 3/Yellow Alarm Detect B/O 77
Address-Data 4/Idle Code Detection B/O 76
Address-Data 5/Parity Error Detect B/O 75
Address-Data 6/Line Code Violation B/O 74
Address-Data 7/Frame Bit Error B/O 73
Address Latch Enable/Parallel Input Enable
Chip Select/Alarm 0
Read*/Alarm 1
Write*/Cycle Redundancy Check 32
Monitor/Microprocessor*
I 69
I 66
I 67
I 68
I 63
AD[0]/LOS
TESTO
AD[1]/OOF
AD[2]/AIS
AD[3]/YEL
AD[4]/IDLE
Microprocessor
Interface
AD[5]/PAR
AD[6]/LCV
AD[7]/FRMERR
CNTINT/LINELB
DLINT/SOURCELB
ALE/PAREN
CS/ALM0
RD*/ALM1
WR*/CRC32
MON/MIC*
37 O Test Out
64 _{O/I Counter Interrupt/Line Loopback}
65 _{O/I Data Link Interrupt/Source Loopback}
B = Bidirectional, I = Input, O = Output
100441E
Conexant
1-7