CN8330 Datasheet, PDF (29/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
2.0 Functional Description
2.3 Transmitter Operation
2.3 Transmitter Operation
The transmitter circuit is synchronized to the transmit input data by an external
synchronization signal. The external synchronization signal sets the M-frame
reference for transmitted signals.
2.3.1 Input and Synchronization
The input to the transmitter consists of the transmit serial data input (or the PPDL
transmitter data), transmit clock, and transmit M-frame sync signal. An M-frame
sync signal output is available on the TXSYO pin to synchronize external
circuitry, if desired. If an input sync is not provided, the CN8330 generates a sync
internally whose position is indicated by TXSYO. In this case, the sync input
should be grounded. The TDAT[7]/TXSYI is sampled on the rising edge of
TXCKI and TDAT[6]/TXDATI is sampled by the falling edge of TXCKI.
2.3.2 DS3 Mode
The input bits are synchronized to the M-frame sync signal, which can either be
externally provided or taken from the M-frame sync signal that is internally
generated. Serial input data on TDAT[6]/TXDATI must contain bit positions for
the overhead bits, although these are not used unless external insertion is enabled.
The clock frequency is nominally 44.736 MHz and the transmit data input is
sampled on the falling edge of the clock signal. The path delay of the transmitter
from the serial data input to the positive and negative outputs is six cycles of the
transmit clock. This delay includes B3ZS/HDB3 coding. The delay from the
serial data input to the NRZ output is two clock cycles and the coding delay of the
B3ZS encoder is four clock cycles.
100441E
Conexant
2-7