CN8330 Datasheet, PDF (90/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

Appendix A Multimegabit HDLC Formatter
A.3 PPDL Transmitter
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
A.3 PPDL Transmitter
The PPDL transmitter is enabled by setting the Parallel Data Enable bit [ParaEn;
CR04.3] in the Feature Control Register [CR04;0x04]. The PPDL formatter is
controlled by signals applied on the SNDMSG and SNDFCS pins. Byte-wide
data is provided on the TDAT[7:0]. Optional HDLC formatting with 16-bit or
32-bit FCSs are provided.
Transmitter operation is controlled by the SNDMSG and SNDFCS pins. If no
message is in progress (SNDMSG and SNDFCS both low), idle flags (01111110)
are continuously transmitted in the data stream. Setting SNDMSG high initiates
message transmission. Data bytes and control signals are provided in response to
the rising edge of the transmit byte clock TXBCK and are sampled internally after
the falling edge. The data and controls should be held for a full period of
TXBCK. The least significant bit of the transmitted bytes is applied to TDAT[0]
and the most significant to TDAT[7]; transmission is least significant bit first.
The transmitter performs automatic zero stuffing for transparency and FCS
calculation for the data. The message must be an integral number of bytes in
length. The FCS is 16 or 32 bits in length depending on the setting of the 32-bit
CRC Select control bit [CRC32;CR05.2] in the PPDL Control Register
[CR05;0x05]. If this bit is low, the FCS is calculated with the polynomial:
x¹⁶+x¹²+x⁵+1. If a 32-bit CRC is selected by setting the CRC32 high, then
SNDFCS shown in Figure A-4 must be high for 4 cycles of the transmit byte
clock and the FCS is calculated with the polynomial:
x³²+x²⁶+x²³+x²²+x¹⁶+x¹²+x¹¹+x¹⁰+x⁸+x⁷+x⁵+x⁴+x²+x+1
The FCS is transmitted by setting both the SNDMSG and SNDFCS pins high
after the last data byte has been transmitted. SNDFCS should be high for 2 byte
clocks in 16-bit FCS mode and for 4 byte clocks in 32-bit FCS mode. An abort
sequence may be transmitted by setting SNDFCS high while SNDMSG is set low.
Timing for the transmit operation is shown in Figure A-4.
Figure A-4. PPDL Transmitter Timing
TXCKI
TXBCK
TDAT[7:0]
SNDMSG
SNDFCS
Data
Data
A-6
Conexant
100441E