CN8330 Datasheet, PDF (52/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

2.0 Functional Description
2.4 Receiver Operation
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
2.4.8 PPDL Receiver
The receiver circuitry contains a PPDL receiver for the payload portion of the
CN8330 data that is activated when the ParaEn bit in the Feature Control Register
is set. This receiver performs idle flag detection, stuffed zero deletion, and FCS
checking on the incoming data stream. The recovered data bytes are presented on
RDAT[7:0] and are valid on both the rising and falling edges of
RXBCK/RXGAPCK. The LSB is on RDAT[0] and the MSB on
RDAT[7]/TXNRZ; the LSB is the first received from the serial input. If the
payload stream contains idle flags, the IDLE pin will be high and the flags will be
present on RDAT[7:0]. If a valid FCS is received at the end of the message block,
the VALFCS/TXOVH pin will be active high while IDLE/FRMCAR is high. At
the start of the next message, both indications will go low until the end of the
incoming message has been received. If a bad FCS is received, IDLE/FRMCAR
will go high and VALFCS/TXOVH will remain low. If VALFCS/TXOVH goes
high and IDLE/FRMCAR does not, an abort sequence was received in the data. If
there is only one flag received between incoming packets, there will be only one
RXBCK/RXGAPCK pulse present while IDLE/FRMCAR is high. If the 32-bit
CRC Select bit (CRC32;CR05.2) is low, the FCS is checked with the polynomial:
x¹⁶+x¹²+x⁵+1
If 32-bit CRC is selected by setting the CRC32 bit high, then the FCS is
checked with the polynomial:
x³²+x²⁶+x²³+x²²+x¹⁶+x¹²+x¹¹+x¹⁰+ x⁸+x⁷+x⁵+x⁴+x²+x+1
2-30
Conexant
100441E