CN8330 Datasheet, PDF (30/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

2.0 Functional Description
2.3 Transmitter Operation
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
If the TDAT[7]/TXSYI M-frame sync signal is provided, it is sampled on the
rising edge of TXCKI and should have a low-to-high transition from the last bit of
the M-frame (bit 680 of subframe 7) to the X1 bit (bit 1 of subframe 1). TXSYO
is clocked out by the rising edge of TXCKI and may be used for synchronization
of external circuitry. Serial data may alternatively be provided in response to the
TXBCK/TXGAPCK pin without the need for providing frame synchronization or
overhead bit slots. The gapped clock output is a gated version of TXCKI with one
pulse gapped for each overhead bit position (one pulse every 85 clock cycles). A
transmit overhead VALFCS/TXOVH bit position indicator pulse is available
when the PPDL is not selected. This pulse is clocked out on the falling edge of
TXCKI and may be of use for providing overhead bits externally. A timing
diagram is presented in Figure 2-4 with propagation delays shown as negligible.
Refer to the Electrical and Mechanical Specifications chapter for actual
propagation delay specifications.
Figure 2-4. Transmitter Timing for Serial DS3 Mode
TXCKI
VALFCS/
TXOVH
TXBCK/
TXGAPCK
TXSYO
TDAT[6]/TXDATI
(Serial In)
Low During Subframe 7
F4
84 Info Bits
X1
84 Info Bits
TDAT[7]/TXSYI
(Sync In)
Subframe 7
Subframe 1
Figure 2-5 illustrates the transmitter timing for the parallel DS3 mode. This
mode is enabled by setting the Parallel Data Enable bit [ParaEn;CR04.3] in the
Feature Control Register and setting the Disable PPDL Transparency bit
[DisPPDL;CR05.1] in the PPDL Control Register [CR05;0x05]. The SNDMSG
pin should be tied high and the SNDFCS tied low to ensure that flags or FCS
bytes are not transmitted.
2-8
Conexant
100441E