CN8330 Datasheet, PDF (23/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

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2.0 Functional Description
2.1 Overview
2.1.1 Brief Block Description
A block diagram of the circuit is illustrated in Figure 2-1. The receive
B3ZS/HDB3 signal is decoded and the bipolar input is converted to a unipolar,
clocked serial data stream. Frame bit content is checked and the overhead bit data
links and alarms are extracted. The receive clock is provided at the receiver output
(RXCLK). The data is also connected to a Payload Parallel Data Link (PPDL)
receiver that decodes message blocks using the High-Level Data Link Control
(HDLC) format (Refer to Appendix A in this document for a description of the
HDLC formatter). The recovered data bytes are provided on a parallel output port
with a byte clock. The PPDL receiver can also be programmed to operate in
nibble mode or transparently without HDLC formatting.
A First In First Out (FIFO) memory buffer in the receive signal path can be
enabled to reduce the jitter on the incoming data. The receive data is clocked into
the FIFO buffer after bipolar decoding. The FIFO buffer provides a Voltage
Controlled Oscillator (VCO) control signal to an external clock recovery circuit.
A dejittered clock (RXCKI) from the VCO is then used to read the data from the
FIFO buffer to the remaining receiver circuitry.
The transmitter is capable of sending either serial data from an external pin, or
byte- or nibble-oriented data from the PPDL data port. DS3 overhead bits or E3
Frame Alignment Signal (FAS) bits are automatically inserted. Parallel data can
be formatted with idle flags, zero stuffing for transparency, and a selectable 16- or
32-bit Frame Check Sequence (FCS). Bytes or nibbles without HDLC formatting
can also be transmitted. The transmitter is able to send AIS, idle code, yellow
alarm, and all-ones signals. DS3 C-bits (or E3 N-bits) can be optionally inserted
into the data stream from an external source.
LAPD (Link Access Procedure-D) receiver and transmitter circuitry is
provided for the terminal data link in DS3 C-bit parity format and the E3 mode. In
C-bit mode, the three C-bits in subframe 5 of the M-frame are used for the
terminal data link. In E3 mode, the N-bit is used for the terminal data link.
The microprocessor interface or external outputs monitors all status
indications in the received signal. For both DS3 and E3 modes, indications
include AIS, all-ones, and yellow alarm detection; and Out-of-Frame (OOF) and
frame bit error counting. In addition, loss of signal, idle code, and parity error
detection; line code violation (LCV), path parity, and FEBE event counting; and
parity and X-bit disagreement counting are provided for DS3 mode. The received
DS3 C-bits (or E3 N-bits) are available on an external pin to provide visibility for
external processing, if necessary.
100441E
Conexant
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