CN8330 Datasheet, PDF (60/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

3.0 Registers
3.1 Control Registers
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
ExtOvh
ExtCBit
E3Frm
CBitP/DL
External Overhead Insert—Set to a 1 to enable insertion of the overhead bits (DS3: X, P, M,
and F or E3: FAS, A, and N) from the transmit serial data stream.
External C-Bit Insert—Used to control insertion of data in the C-bit or N-bit positions of the
transmit data stream. In DS3 mode, the C-bits are controlled as follows:
U
C-Bit Parity Mode Ext. C-Bit Insert
C-Bit Source
0
0
Serial Data Stream
0
1
CBITI Pin
1
0
All C-Bits Internally Generated
1
1
Internal Except CP and FEBE from CBITI Pin
In E3 mode, External C-Bit Insert controls insertion of data in the N-bit position of the E3
data stream. The N-bit will come from the CBITI pin when ExtCBit is high, and from the
terminal data link transmitter when ExtCBit is low.
E3 Framing Mode—Enables the E3 mode framing and transmission circuitry. This control bit has
priority over the C-Bit Parity Mode/Enable DLINT bit. Framing insertion and recovery is
performed as specified in ITU–T G.751
C-Bit Parity Mode/Enable DLINT—Selects which type of framing is present on the
transmitted DS3 signal. If this bit is low, then the basic DS3 framing mode is used. If this
control bit is high, then the C-bit positions are used for the FEBE, FEAC, terminal data link,
path parity, and mode indicator bits as defined in T1.107a-1989. When the E3 framing mode
bit is high, this bit enables interrupts on the DLINT/SOURCELB output pin.
3-2
Conexant
100441E