CN8330 Datasheet, PDF (16/101 Pages) Conexant Systems, Inc – DS3/E3 Framer with 52 Mbps HDLC Controller

1.0 Product Description
1.1 Pin Descriptions
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
Figure 1-3. CN8330 Framer Functional Logic Diagram - 68-Pin PLCC
Rx Bipolar Pos
Rx Bipolar Neg
Rx Line Clock In
Dejittered Clock In
FIFO Enable
I 13
I 14
I 15
I 16
I 11
RXPOS
RXNEG
DS3CKI
RXCKI
FIFEN
Receiver
Section
RXDAT
RXMSY
RXCLK
CBITO
RXCCK/TXNRZ
RDAT[7]/TXNRZ
20 O Rx Serial Data
21 O Rx M-Sync
22 O Rx Clock
37 O Rx C/N Bit Serial Out
38 O Rx C/N-Bit Clock Out/TxNRZ
34 O Rx Data Bit MSB/TxNRZ
RDAT[6]/RXOVH 33 O Rx Data Bit 6/RX Overhead
Tx Clock In I ⁵⁸ TXCKI
RDAT[5]/LCVCAR 32 O Rx Data Bit 5/ Line Code Violation Carry
Tx C/N Bit Serial In I ⁴⁵ CBITI
RDAT[4]/FRMERR 31 O Rx Data Bit 4/Frame Bit Error
Tx Data Bit MSB/Tx M-Sync In I ⁵⁶ TDAT[7]/TXSYI
RDAT[3]/IDLE 30 O Rx Data Bit 3/Idle Code Detection
Tx Data Bit 6/Tx Serial Data In I ⁵⁵ TDAT[6]/TXDATI
RDAT[2]/AIS 29 O Rx Data Bit 2/Alarm Indication Signal
Tx Data Bit 5/Tx Encoder In I ⁵⁴ TDAT[5]/TXENCI
RDAT[1]/OOF 28 O Rx Data Bit 1/Out of Frame
Tx Data Bit 4/LCV Error In I ⁵³ TDAT[4]/LCVERRI
RDAT[0]/LOS 27 O Rx Data Bit LSB/Loss of Signal
Tx Data Bit 3 I ⁵⁰ TDAT[3]
IDLE/FRMCAR 24 O Idle Data Rcvd/Frame Carry
Tx Data Bit 2 I ⁴⁹ TDAT[2]
VALFCS/TXOVH 25 O Valid FCS Rcvd/TX Overhead
Tx Data Bit 1 I ⁴⁸ TDAT[1]
VCO 12 O Voltage-Controlled Oscillator Output
Tx Data Bit LSB I ⁴⁷ TDAT[0]
RXBCK/RXGAPCK 23 O Rx Byte Clock/Gapped Clock
Send FCS I ⁴³ SNDFCS
Send Message I ⁴² SNDMSG
Parallel Data Only Select I ⁴⁴ PPDLONLY
Test In I ⁶⁰ TESTI
Initialization I ¹⁹ INIT*
TXBCK/TXGAPCK
TXCCK
Transmitter _TXPOS
Section _TXNEG
TXSYO
TCLKO
57 O Tx Byte Clock/Gapped Clock
46 O Tx C/N Bit Clock
40 O Tx Bipolar Pos
39 O Tx Bipolar Neg
59 O Tx M-Sync Out
18 O Tx Clock Out
Address-Data 0/Loss of Signal B/O 9
Address-Data 1/Out of Frame B/O 8
Address-Data 2/Alarm Indication Signal B/O 7
Address-Data 3/Yellow Alarm Detect B/O 6
Address-Data 4/Idle Code Detection B/O 5
Address-Data 5/Parity Error Detect B/O 4
Address-Data 6/Line Code Violation B/O 3
Address-Data 7/Frame Bit Error B/O 2
Address Latch Enable/Parallel Input Enable
Chip Select/Alarm 0
Read*/Alarm 1
Write*/Cycle Redundancy Check 32
Monitor/Microprocessor*
I 67
I 64
I 65
I 66
I 61
AD[0]/LOS
TESTO
AD[1]/OOF
AD[2]/AIS
AD[3]/YEL
AD[4]/IDLE
Microprocessor
Interface
AD[5]/PAR
AD[6]/LCV
AD[7]/FRMERR
CNTINT/LINELB
DLINT/SOURCELB
ALE/PAREN
CS/ALM0
RD*/ALM1
WR*/CRC32
MON/MIC*
41 O Test Out
62 _{O/I Counter Interrupt/Line Loopback}
63 _{O/I Data Link Interrupt/Source Loopback}
B = Bidirectional, I = Input, O = Output
1-6
Conexant
100441E