CMX983 Datasheet, PDF (83/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
15.4 Timing Diagrams
Test Load A
Device
Under Test
C1
DV_SS
DV_DD
Test Load B
R1
Device
Under Test
R2
C2
DV_SS DV_SS
R1 = 1.2 kΩ
R2 = 1 kΩ
C1 = 5 pF (min), 30 pF (max)
C2 = 5 pF
C1, C2 include jig
Figure 30 AC Test Load for Digital Outputs
CMX983
CSN
SCLK
Address
…
Write Data
CDATA
7
6
5
4
3
2
1
0
15 14
76
… 3210
Read Data
RDATA Hi-Z
= Level undefined
or not important
15 14
76
…
3210
…
…
765 …
…
CSN
SCLK
tCSOFF
70% IOVDD
30% IOVDD
tCSE
tCK
tCH
tCL
tCDS
tCDH
CDATA
tRDV
tLOZ
RDATA
tCSH
tRDV
tHIZ
Figure 31 C-BUS Timings
 2015 CML Microsystems Plc
83
D/983/6