CMX983 Datasheet, PDF (62/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
Adding bleed or leakage current will increase the average phase error because it shifts the position of the N-
divider output with respect to the R-divider output. The amount of this shift, as described in section 12.3.1, is
𝑡_{𝑜𝑓𝑓𝑠𝑒𝑡}
≅
𝑅_{𝑑𝑖𝑣}(𝐼_{𝑏𝑙𝑒𝑒𝑑} + 𝐼_{𝑙𝑒𝑎𝑘𝑎𝑔𝑒} )
𝑓_{𝑀𝐶𝐿𝐾} 𝐼_{𝐶𝑃1}
For the purpose of calculations the average “in-lock” phase error is approximately
𝑡_{𝑝ℎ𝑎𝑠𝑒_𝑒𝑟𝑟}
≅
√𝑡_{𝑜𝑓𝑓𝑠𝑒𝑡} ²
+
2²
(𝑓_{𝑉𝐶𝑂} )
In order for the lock detector capacitor voltage to increase when the PLL is in lock, the average charge
supplied to the capacitor on each cycle must be greater than the charge removed. To achieve this, the
discharge factor set by PLL1_LOCKDET bits 6-4 should set to:
𝑑𝑖𝑠𝑐ℎ𝑎𝑟𝑔𝑒_𝑟𝑎𝑡𝑒
≈
1
𝑀
(𝑓_{𝑀𝐶𝐿𝐾}^{í µí µí±…í±¡}_{í µí µí±í±‘â„Ží µí±–í µí µí±£í±Ží µí± í µí±’_𝑒𝑟𝑟}
−
1)
where M is the ratio (when in lock) of the charge added to the capacitor to the charge removed on each phase
detector cycle. A good rule is to make M=4, although this value can be adjusted to achieve reliable lock
detector operation.
 2015 CML Microsystems Plc
62
D/983/6