CMX983 Datasheet, PDF (75/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
This bit determines the behaviour of DAC0 during a ramp operation when a C-BUS command is
issued that reverses the direction of the ramp, i.e. issuing an AUXDAC_UP command while the DAC
is ramping down, or issuing an AUXDAC_DOWN command while the DAC is ramping up. When this
bit is set to 0, the ramp direction reverses immediately. When this bit is set to 1, the ramp direction
reverses only when the currently active ramp operation completes.
AUXDAC_DATA0 Register b13: Ramp hold
Set this bit to 1 to pause a ramp up, ramp down or ramp cycle operation; this freezes the DAC0
output. Setting this bit to 0 allows the ramp function to continue.
AUXDAC_DATA0 Register b12: DAC0 select
This bit controls the multiplexer at the input to DAC0. When this bit is set to 1, the DAC RAM output
register is connected to DAC0 and C-BUS writes to the DAC RAM are disabled. When this bit is set to
0, the AUXDAC_DATA0 register is connected to DAC0 and any active ramp operation is immediately
terminated.
AUXDAC_DATA1-8 Register b14-12: Reserved, set to 0
AUXDAC_DATA0-8 Register b11-10: Reserved, set to 0
AUXDAC_DATA0-8 Register b9-0: DAC0 – DAC8 data
The least significant 10-bit values in registers AUXDAC_DATA1 – AUXDAC_DATA8 are driven
directly into the corresponding auxiliary DACs. The least significant 10-bit value in register
AUXDAC_DATA0 is multiplexed with the output of the ramp circuit before being driven into DAC0;
this multiplexer is controlled by AUXDAC_DATA0 bit 12.
An example of the Aux DAC RAM contents for a raised cosine ramp profile is shown in Figure 29.
Aux DAC RAM contents (hexadecimal)
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
000 001 003 006 00A 010 017 01F 028 033 03E 04B 059 068 078 089
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
09A 0AD 0C1 0D5 0EA 100 116 12D 145 15D 175 18E 1A7 1C0 1D9 1F3
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
20C 226 23F 258 271 28A 2A2 2BA 2D2 2E9 2FF 315 32A 33E 352 365
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
376 387 397 3A6 3B4 3C1 3CC 3D7 3E0 3E8 3EF 3F5 3F9 3FC 3FE 3FF
Figure 29 Aux DAC RAM contents example
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