CMX983 Datasheet, PDF (65/93 Pages) CML Microcircuits – Programmable Channel Filter

Analogue Front End (AFE) for Digital Radio
CMX983
AUXADC_CLK - $62: 16-bit Write
Reset value = $0000
Bit:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Aux ADC clock divide
Timer coarse divide
Timer fine divide
AUXADC_CLK b15-10: Aux ADC clock divide
These bits hold the prescaler value P that determines the frequency of the auxiliary ADC clock
‘AuxADCClk’. The value P can be set to between 1 and 64 (000000 = 64); the frequency of
AuxADCClk is given by:
f _AuxADCClk

f _CLK
2 P
AuxADCClk should be set to a frequency of between 1MHz and 2MHz. Each individual ADC
conversion takes 11 periods of AuxADCClk to perform, plus one extra cycle of CLK to store the result
in the associated data register. If there are N channels enabled, then a convert sequence will be
completed in a time given by:

T_Convert  N_

11
f _AuxADCClk

1
f _CLK

If the AUXADC_PWRUP register is loaded with a value greater than 0, the convert sequence will be
lengthened by that number of AuxADCClk cycles.
AUXADC_CLK b9-7: Timer coarse divide
AUXADC_CLK b6-0: Timer fine divide
The Aux ADC timer determines the rate at which convert sequences are started in continuous convert
mode. The coarse divide can be set to a value between 0 and 7, and the fine divide can be set to
between 1 and 128 (0000000 = 128). The timer interval is given by this expression:
T_Timer

4^CoarseDivide  FineDivide
f _CLK
For instance, if the coarse divide is set to 2 (010) and the fine divide is set to 125 (1111101) then the
timer interval will equal 4²x125 = 2000 cycles of CLK.
The timer period T_Timer should be set to a value greater than the convert sequence time T_Convert, unless
back-to-back convert sequences are required in which case set the coarse divide to 000 and the fine
divide to 0000001.
AUXADC_PWRUP - $63: 16-bit Write
Reset value = $0000
Bit:
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Pwrup
enab
0
0
0
0
Power up coarse
divide
Power up fine divide
AUXADC_PWRUP b15: Power-up enable
 2015 CML Microsystems Plc
65
D/983/6